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    • 61. 发明专利
    • MANUFACTURE OF MULTILAYER CERAMIC WIRING BOARD
    • JPH0823169A
    • 1996-01-23
    • JP15443494
    • 1994-07-06
    • HITACHI LTD
    • YAMAGUCHI AKIRAKATO MASAYOSEKIHASHI MASAO
    • H05K1/03H05K3/46
    • PURPOSE:To reduce short circuits or openings of thin film patterns formed on a substrate by making small a void diameter in the outermost layer or in the surface layer of a multilayer ceramic wiring board. CONSTITUTION:Green sheets, whose manufacturing differs for the outermost layer or a surface layer 1 and an internal layer 2, are used. Each green sheet is treated with a through hole 3, and the like. After a prescribed number of laminates are bonded and sintered to make a void 4 in the outermost layer or the surface layer 1 smaller than the void 4 in the inner layer 2. For decreasing the void 4 in the outermost layer or the surface layer 1, there are methods such as dry mixing and adding of powder materials or reduction of the blending rate of flux and a combination of both. Consequently, by making smaller the void diameter in the outermost layer or the surface layer 1 of the multilayer ceramic wiring board, short-circuits and inferior openings of a thin film pattern formed on the multilayer ceramic wiring board can be prevented.