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61. 发明授权

US08635381B2 System, method and computer program product for monitoring memory access 失效
标题翻译：用于监控内存访问的系统，方法和计算机程序产品
公开(公告)号：US08635381B2
公开(公告)日：2014-01-21
申请号：US12869591
申请日：2010-08-26
申请人： Richard L. Arndt , Karthick Rajamani , Jeffrey A. Stuecheli
发明人： Richard L. Arndt , Karthick Rajamani , Jeffrey A. Stuecheli
IPC分类号： G06F3/00
CPC分类号： G06F11/3485 , G06F2201/88
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring, by a plurality of memory controllers, access to a memory unit, wherein each memory controller is associated with a different range of memory addresses of the memory unit, and wherein each memory controller monitors access for its associated range of memory addresses. The method also includes updating an incrementor with access data corresponding to accesses to the memory unit, wherein each memory controller updates the access data based on access of its associated range of memory addresses. The method further includes storing, by each respective memory controller, the updated access data in a cache corresponding to the respective range of memory addresses and, responsive to the updated access data for a respective range of memory addresses exceeding a threshold, storing the access data for the respective range of memory addresses in memory unit.
摘要翻译：根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。该方法包括通过多个存储器控制器监视对存储器单元的访问，其中每个存储器控制器与存储器单元的存储器地址的不同范围相关联，并且其中每个存储器控制器监视对其相关联的存储器地址范围的访问。该方法还包括使用与对存储器单元的访问相对应的访问数据来更新增量器，其中每个存储器控制器基于其相关联的存储器地址范围的访问来更新访问数据。该方法还包括由每个相应的存储器控制器将更新的访问数据存储在与存储器地址的相应范围相对应的高速缓存中，并且响应于对于超过阈值的存储器地址的相应范围的更新的访问数据，存储访问数据对于存储器单元中的各个存储器地址范围。

62. 发明申请

US20130128682A1 MEMORY SYSTEM WITH DYNAMIC REFRESHING 有权
标题翻译：具有动态刷新记忆系统
公开(公告)号：US20130128682A1
公开(公告)日：2013-05-23
申请号：US13298587
申请日：2011-11-17
申请人： Joab D. Henderson , Hillery C. Hunter , Warren E. Maule , Jeffrey A. Stuecheli
发明人： Joab D. Henderson , Hillery C. Hunter , Warren E. Maule , Jeffrey A. Stuecheli
IPC分类号： G11C11/402
CPC分类号： G11C11/40611 , G11C2211/4061
摘要： An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.
摘要翻译：提供的实施例是具有动态刷新的存储器系统，其包括具有存储器单元的存储器件。该系统还包括与存储器设备和存储器控制器通信的刷新模块，该刷新模块被配置用于从存储器控制器接收刷新命令，并且响应于接收到所述存储器控制器来刷新存储器设备中的多个存储器单元刷新命令。响应于接收到刷新命令刷新的存储器单元的数量响应期望带宽特性和期望延迟特性中的至少一个。

63. 发明授权

US08131974B2 Access speculation predictor implemented via idle command processing resources 失效
标题翻译：通过空闲命令处理资源实现访问推测预测器
公开(公告)号：US08131974B2
公开(公告)日：2012-03-06
申请号：US12105427
申请日：2008-04-18
申请人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/507 , G06F2212/6022 , G06F2212/6024 , Y02D10/13
摘要： An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.
摘要翻译：提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。可以选择其存储区域包括第一地址的FSM。可以从所选择的FSM获得用于存储器区域的历史信息。历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。

64. 发明授权

US08122222B2 Access speculation predictor with predictions based on a scope predictor 失效
标题翻译：基于范围预测器访问具有预测的投机预测因子
公开(公告)号：US08122222B2
公开(公告)日：2012-02-21
申请号：US12105360
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0831 , G06F2212/1041 , G06F2212/507 , G06F2212/6022 , G06F2212/6024
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.
摘要翻译：访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和范围预测器。可以确定接收第一数据请求的存储器控制器是否是本地的第一数据请求的源。可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为必要。

65. 发明申请

US20080082754A1 METHOD AND CACHE SYSTEM WITH SOFT I-MRU MEMBER PROTECTION SCHEME DURING MAKE MRU ALLOCATION 有权
标题翻译：在制作MRU分配过程中使用软I-MRU成员保护方案的方法和缓存系统
公开(公告)号：US20080082754A1
公开(公告)日：2008-04-03
申请号：US11538091
申请日：2006-10-03
申请人： Robert H. Bell , Jeffrey A. Stuecheli
发明人： Robert H. Bell , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/126
摘要： A caching mechanism implementing a “soft” Instruction-Most Recently Used (I-MRU) protection scheme whereby the selected I-MRU member (cache line) is only protected for a limited number of eviction cycles unless that member is updated/utilized during the period. An update or access to the instruction restarts the countdown that determines when the cache line is no longer protected as the I-MRU. Accordingly, only frequently used Instruction lines are protected, and old I-MRU lines age out of the cache. The old I-MRU members are evicted, such that all the members of a congruence class may be used for data. The I-MRU aging is accomplished through a counter or a linear feedback shift register (LFSR)-based “shootdown” of I-MRU cache lines. The LFSR is tuned such that an I-MRU line will be protected for a pre-established number of evictions.
摘要翻译：实现“软”指令 - 最近使用（I-MRU）保护方案的缓存机制，由此所选择的I-MRU成员（高速缓存行）仅对有限数量的驱逐周期进行保护，除非该成员在期。对该指令的更新或访问将重新启动倒数计时，以确定高速缓存行何时不再受I-MRU的保护。因此，只有经常使用的指令行被保护，并且旧的I-MRU线老化在高速缓存之外。旧的I-MRU成员被驱逐出来，使得一致等级的所有成员都可以用于数据。 I-MRU老化通过I-MRU高速缓存线的计数器或线性反馈移位寄存器（LFSR）的“下降”来实现。调整LFSR，使得I-MRU线路将受到预先确定的驱逐次数的保护。

66. 发明授权

US09632954B2 Memory queue handling techniques for reducing impact of high-latency memory operations 有权
公开(公告)号：US09632954B2
公开(公告)日：2017-04-25
申请号：US13290702
申请日：2011-11-07
申请人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1626 , G06F13/16
摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

67. 发明授权

US08909690B2 Performing arithmetic operations using both large and small floating point values 有权
标题翻译：使用大和小浮点值执行算术运算
公开(公告)号：US08909690B2
公开(公告)日：2014-12-09
申请号：US13324025
申请日：2011-12-13
申请人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
发明人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译：提供了用于在数据处理系统中执行浮点算术运算的机构。接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值，至少一个浮点操作数的尾数的位的范围。基于向量值和多个浮点操作数，生成用于浮点运算的结果值。

68. 发明授权

US08539146B2 Apparatus for scheduling memory refresh operations including power states 有权
标题翻译：用于调度包括电源状态的存储器刷新操作的装置
公开(公告)号：US08539146B2
公开(公告)日：2013-09-17
申请号：US13305200
申请日：2011-11-28
申请人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40615 , G06F13/1694 , Y02D10/14
摘要： A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.
摘要翻译：公开了一种用于在一级存储器件上执行刷新操作的方法。在完成存储器操作之后，确定刷新积压计数值是否小于预定值，并且存储器件的等级被断电。如果刷新积压计数值小于预定值并且存储器件的等级被断电，则将空闲计数阈值设置为最大值，使得将在最大延迟时间之后执行刷新操作。如果刷新积压计数值不小于预定值或存储器件的等级不处于掉电状态，则基于空闲延迟功能的斜率来设置空闲计数阈值，使得刷新操作将相应地执行。

69. 发明申请

US20130212330A1 MEMORY RECORDER QUEUE BIASING PRECEDING HIGH LATENCY OPERATIONS 有权
标题翻译：内存记录器排队高效率运行
公开(公告)号：US20130212330A1
公开(公告)日：2013-08-15
申请号：US13371906
申请日：2012-02-13
申请人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问针对第一个内存排名的操作。该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

70. 发明授权

US08489807B2 Techniques for performing refresh operations in high-density memories 失效
标题翻译：在高密度存储器中执行刷新操作的技术
公开(公告)号：US08489807B2
公开(公告)日：2013-07-16
申请号：US12959637
申请日：2010-12-03
申请人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
发明人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40603
摘要： Techniques for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.
摘要翻译：公开了用于执行刷新操作的技术。响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

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