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61. 发明授权

US06498062B2 DRAM access transistor 有权
标题翻译： DRAM存取晶体管
公开(公告)号：US06498062B2
公开(公告)日：2002-12-24
申请号：US09842788
申请日：2001-04-27
申请人： D. Mark Durcan , Roger Lee
发明人： D. Mark Durcan , Roger Lee
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10811 , H01L27/10823 , H01L29/66621 , H01L29/7834
摘要： A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclose. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to the adjacent and elevated silicon nitride.
摘要翻译：公开了一种形成具有凹陷栅结构的存储器件诸如DRAM存取晶体管的方法。首先在半导体衬底上形成用于隔离的场氧化物区域，随后在氮化硅层中图案化并蚀刻晶体管沟槽。然后与晶体管沟槽相邻的场氧化物区域是凹进的，因此随后沉积的多晶硅用于栅极结构形成可以相对于相邻和升高的氮化硅进行抛光。

62. 发明授权

US06333240B1 Method of spacing a capacitor from a contact site 失效
标题翻译：将电容器与接触部位间隔开的方法
公开(公告)号：US06333240B1
公开(公告)日：2001-12-25
申请号：US09652497
申请日：2000-08-31
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

63. 发明授权

US6159790A Method of controlling outdiffusion in doped three-dimensional film by using angled implants 有权
标题翻译：通过使用倾斜植入物控制掺杂三维膜中的扩散扩散的方法
公开(公告)号：US6159790A
公开(公告)日：2000-12-12
申请号：US310489
申请日：1999-05-12
申请人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

64. 发明授权

US08124491B2 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US08124491B2
公开(公告)日：2012-02-28
申请号：US12547197
申请日：2009-08-25
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

65. 发明授权

US07935950B2 Controllable ovonic phase-change semiconductor memory device and methods of programming the same 有权
标题翻译：可控的卵子相变半导体存储器件及其编程方法
公开(公告)号：US07935950B2
公开(公告)日：2011-05-03
申请号：US11833034
申请日：2007-08-02
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L47/00 , H01L29/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的超声相变半导体存储器件及其编程方法。这种存储器件包括包括非平行侧壁的下电极。绝缘材料覆盖下电极，使得下电极的上表面露出。在一个实施例中，绝缘材料和下电极可以具有共面上表面。在另一个实施例中，下电极的上表面在绝缘材料的凹槽内。硫族化物材料和上电极形成在下电极的上表面上。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

66. 发明授权

US07687408B2 Method for integrated circuit fabrication using pitch multiplication 失效
标题翻译：使用音调倍数的集成电路制作方法
公开(公告)号：US07687408B2
公开(公告)日：2010-03-30
申请号：US11683518
申请日：2007-03-08
申请人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
发明人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.
摘要翻译：集成电路的阵列和周边中的不同尺寸的特征在单个步骤中在衬底上图案化。特别地，组合两个单独形成的图案的混合图案形成在单个掩模层上，然后转移到下面的基底。单独形成的图案中的第一个通过间距倍增形成，并且通过常规光刻形成第二个单独形成的图案。单独形成的图案中的第一个包括低于用于形成第二个单独形成的图案的光刻工艺的分辨率的线。这些线通过在光致抗蚀剂上形成图案然后将该图案刻蚀成无定形碳层而制成。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁盘。然后去除无定形碳，留下侧壁间隔物作为掩模图案。因此，间隔物形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模。保护材料沉积在间隔物周围。使用硬掩模进一步保护间隔物，然后在硬掩模上形成并图案化光致抗蚀剂。光致抗蚀剂图案通过硬掩模转印到保护材料上。然后将由间隔物和临时材料制成的图案转移到下面的无定形碳硬掩模层。具有不同尺寸特征的图案然后被转移到下面的基底。

67. 发明授权

US07253430B2 Controllable ovonic phase-change semiconductor memory device 失效
标题翻译：可控超声相变半导体存储器件
公开(公告)号：US07253430B2
公开(公告)日：2007-08-07
申请号：US10644685
申请日：2003-08-20
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L47/00 , H01L29/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的相位相移型半导体存储器件及其形成方法。这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。在下电极上施加绝缘材料，使得尖端的上表面露出。硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

68. 发明授权

US06999339B2 Integrated circuit including sensor to sense environmental data, method of compensating an MRAM integrated circuit for the effects of an external magnetic field, MRAM integrated circuit, and method of testing 有权
标题翻译：集成电路，包括用于感测环境数据的传感器，用于补偿外部磁场效应的MRAM集成电路的方法，MRAM集成电路和测试方法
公开(公告)号：US06999339B2
公开(公告)日：2006-02-14
申请号：US10421201
申请日：2003-04-22
申请人： Mark E. Tuttle , D. Mark Durcan
发明人： Mark E. Tuttle , D. Mark Durcan
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C29/02 , G11C29/028 , G11C2029/5006
摘要： An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.
摘要翻译：集成电路包括操作电路; 被配置为感测环境参数的传感器; 以及耦合到所述传感器和所述操作电路并被配置为影响所述操作电路以至少部分抵消所述环境参数的影响的调节电路。一种测试集成电路的方法包括在集成电路中支持传感器，并使用传感器来感测环境数据。

69. 发明授权

US06897467B2 Controllable ovanic phase-change semiconductor memory device 失效
标题翻译：可控电流相变半导体存储器件
公开(公告)号：US06897467B2
公开(公告)日：2005-05-24
申请号：US10346994
申请日：2003-01-17
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的双相相变半导体存储器件及其形成方法。这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。在下电极上施加绝缘材料，使得尖端的上表面露出。硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

70. 发明授权

US06780732B2 DRAM access transistor 有权
标题翻译： DRAM存取晶体管
公开(公告)号：US06780732B2
公开(公告)日：2004-08-24
申请号：US10270150
申请日：2002-10-15
申请人： D. Mark Durcan , Roger Lee
发明人： D. Mark Durcan , Roger Lee
IPC分类号： H01L2176
CPC分类号： H01L27/10876 , H01L27/10811 , H01L27/10823 , H01L29/66621 , H01L29/7834
摘要： A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclosed. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to the adjacent and elevated silicon nitride.
摘要翻译：公开了一种形成具有凹陷栅极结构的存储器件诸如DRAM存取晶体管的方法。首先在半导体衬底上形成用于隔离的场氧化物区域，随后在氮化硅层中图案化并蚀刻晶体管沟槽。然后与晶体管沟槽相邻的场氧化物区域是凹进的，因此随后沉积的多晶硅用于栅极结构形成可以相对于相邻和升高的氮化硅进行抛光。

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