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61. 发明授权

US06342452B1 Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask 失效
标题翻译：使用介电牺牲层作为掩模制造Si 3 N 4 /多晶硅结构的方法
公开(公告)号：US06342452B1
公开(公告)日：2002-01-29
申请号：US09573352
申请日：2000-05-18
申请人： Philippe Coronel , Pascal Costaganna , Lars Heineck
发明人： Philippe Coronel , Pascal Costaganna , Lars Heineck
IPC分类号： H01L213065
CPC分类号： H01L21/76897 , H01L21/32137 , H01L21/32139
摘要： According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask. A conformal layer of Si3N4 is deposited onto the structure, then anisotropically dry etched until the thin SiO2 layer is exposed to form the Si3N4 spacers. Diffusion regions are formed in the substrate by ion implantation. A layer of BPSG is deposited onto the structure and planarized. Contact holes are formed to expose said diffusion regions and filled with a metal to create borderless metal contacts therewith.
摘要翻译：根据所公开的方法，提供了由涂覆有底部薄SiO 2层，掺杂多晶硅层，难熔金属层和顶部Si 3 N 4覆盖层的硅衬底组成的结构。所述难熔金属和掺杂多晶硅层将在随后的热处理下形成多晶硅化物层。首先，将诸如氮氧化合物的介电材料的牺牲层沉积到该结构上。氮氧化物不受UV辐射的影响，具有优异的保形特性。然后，将光致抗蚀剂材料层沉积到结构上并图案化以形成掩模。现在使用光致抗蚀剂掩模对电介质和顶部Si 3 N 4层进行各向异性蚀刻。将掩模剥离，并使用图案化的介电层作为原位硬掩模将难熔金属和掺杂多晶硅层各向异性地干蚀刻到SiO 2层。将Si3N4的保形层沉积在该结构上，然后各向异性干蚀刻直到薄的SiO 2层暴露以形成Si 3 N 4间隔物。通过离子注入在衬底中形成扩散区。一层BPSG沉积在结构上并平坦化。形成接触孔以暴露所述扩散区域并填充金属以与其形成无边界金属接触。

62. 发明授权

US06297089B1 Method of forming buried straps in DRAMs 失效
标题翻译：在DRAM中形成埋地带的方法
公开(公告)号：US06297089B1
公开(公告)日：2001-10-02
申请号：US09447630
申请日：1999-11-23
申请人： Philippe Coronel , Edith Lattard , Renzo Maccagnan
发明人： Philippe Coronel , Edith Lattard , Renzo Maccagnan
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A conventional initial deep trench structure consists of a patterned Si3N4 pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO2 collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO2 is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO2 is etched at least 6 times faster than the Si3N4 (stopping on the Si3N4 pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6× the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing down to approximately the Si3N4 pad layer surface and finally recessed down to a depth level substantially coplanar with the silicon surface substrate to create a POLY2 stud. The buried strap is formed by the doped region and POLY2 stud. The above method presents significant advantages in terms of product reliability, throughput improvements and process flow simplification.
摘要翻译：常规的初始深沟槽结构由其中形成有深沟槽的经图案化的Si 3 N 4衬垫层包覆的硅衬底组成。沟槽部分地被掺杂多晶硅（POLY1）填充。在所述多晶硅填充物和衬底之间插入电介质膜以形成存储电容器。 TEOS SiO2轴环层共形地涂覆结构的上部。现在，在相同的RIE反应器中进行的两步法中TEOS SiO2被干蚀刻。在第一步中，TEOS SiO2被蚀刻至少比Si3N4快6倍（停止在Si3N4焊盘层上）。在第二步中，操作条件确保部分各向同性的干法蚀刻，优选具有两倍的功率和1.25倍的压力，从而提供6倍的水平速率的垂直蚀刻速率。作为该步骤的结果，沟槽中的硅衬底的上部暴露而不损坏。接下来，将N型掺杂剂注入到硅衬底的上部以产生掺杂区域。沟槽填充有一层掺杂的多晶硅（POLY2），其通过化学机械抛光平坦化到大约Si3N4焊盘层表面，最后凹陷到与硅表面衬底基本上共面的深度级以产生POLY2螺柱。掩埋带由掺杂区域和POLY2螺柱形成。上述方法在产品可靠性，吞吐量改进和工艺流程简化方面具有显着的优势。

63. 发明授权

US5658418A Apparatus for monitoring the dry etching of a dielectric film to a given thickness in an integrated circuit 失效
标题翻译：用于在集成电路中监测电介质膜到给定厚度的干蚀刻的装置
公开(公告)号：US5658418A
公开(公告)日：1997-08-19
申请号：US536900
申请日：1995-09-29
申请人： Philippe Coronel , Jean Canteloup
发明人： Philippe Coronel , Jean Canteloup
IPC分类号： G01B11/06 , C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/66
CPC分类号： H01J37/32935 , H01J37/32972
摘要： Detecting the desired etch end point in the dry etching of a structure that includes a dielectric film formed onto a substrate down to a given thickness Ef. The structure is placed in the chamber of an etching equipment provided with a view-port. A light source illuminates a portion of the structure at a normal angle of incidence through the view-port. The light contains at least two specified wavelengths (L1, L2) whose value is greater than a minimum value equal to 4*N*e (wherein N is the index of refraction and e the thickness error of the dielectric). The reflected light is applied to spectrometers tuned to each specified wavelength, for converting the reflected light into interference signals that are processed and analyzed in a dedicated unit to generate primary signals (S1, S2). An analysis of the primary signals is performed after a predetermined delay. For each wavelength, a pre-selected extremum of the primary signal is detected and a predetermined number of extrema is counted. The counting stops when the last extremum just before Ef is reached. As a result, the distance D between the last extremum and the given thickness is now determined. The etch rate ER is also measured in-situ before the last extremum.
摘要翻译：在包括形成在基底上的电介质膜的结构的干蚀刻中检测所需的蚀刻终点，直到给定的厚度Ef。该结构被放置在设置有视口的蚀刻设备的腔室中。光源以通常的入射角通过视口来照射结构的一部分。光包含至少两个指定波长（L1，L2），其值大于等于4 * N * e的最小值（其中N是折射率，e是电介质的厚度误差）。将反射光应用于调谐到每个指定波长的光谱仪，用于将反射光转换成在专用单元中处理和分析以产生主信号（S1，S2）的干扰信号。在预定延迟之后执行主信号的分析。对于每个波长，检测到主信号的预选极值，并计数预定数量的极值。当到达Ef之前的最后一个极值时，计数停止。结果，现在确定最后极值与给定厚度之间的距离D. 蚀刻速率ER也是在最后极值之前的原位测量的。

64. 发明申请

US20140158334A1 THERMAL MANAGEMENT SYSTEM WITH VARIABLE-VOLUME MATERIAL 审中-公开
标题翻译：具有可变体积材料的热管理系统
公开(公告)号：US20140158334A1
公开(公告)日：2014-06-12
申请号：US14128266
申请日：2012-06-21
申请人： Olivier Dellea , Philippe Coronel , Jérôme Gavillet , Emmanuel Ollier , Helga Szambolics
发明人： Olivier Dellea , Philippe Coronel , Jérôme Gavillet , Emmanuel Ollier , Helga Szambolics
IPC分类号： F28F27/00
CPC分类号： F28F27/00 , F28D15/00 , F28D20/02 , F28F13/00 , F28F2013/005 , F28F2013/008 , G05D23/028 , H01L23/4275 , H01L2924/0002 , H01L2924/00
摘要： A thermal management system configured to be installed between a heat source and a heat sink, including a first heat conductor and a second heat conductor, a thermal switch configured to allow or prevent thermal connection between the first and second heat conductors, the thermal switch including at least one thermally conductive material that can connect the first and second conductors by a change in its volume, and the thermal switch including a controller configured to transfer thermal energy to the phase-change material to change a connection state. The connection is made when the heat source goes above a critical temperature, since the connection enables a heat flux to be established between the heat source and the heat sink.
摘要翻译：一种热管理系统，被配置为安装在热源和散热器之间，包括第一热导体和第二导热体，被配置为允许或防止第一和第二热导体之间的热连接的热开关，热开关包括至少一个能够通过其体积变化连接第一和第二导体的导热材料，并且热开关包括被配置为将热能传递到相变材料以改变连接状态的控制器。当热源超过临界温度时进行连接，因为连接使得能够在热源和散热器之间建立热通量。

65. 发明申请

US20140147583A1 FACILITY AND METHOD FOR DEPOSITING A WIDTH ADJUSTABLE FILM OF ORDERED PARTICLES ONTO A MOVING SUBSTRATE 有权
标题翻译：将有序粒子的宽幅可调整膜放置在移动基板上的设备和方法
公开(公告)号：US20140147583A1
公开(公告)日：2014-05-29
申请号：US14131082
申请日：2012-07-10
申请人： Olivier Dellea , Philippe Coronel , Pascal Fugier
发明人： Olivier Dellea , Philippe Coronel , Pascal Fugier
IPC分类号： B05C19/04 , B05D1/12
CPC分类号： B05C19/04 , B05C11/1002 , B05C11/1036 , B05C19/00 , B05C19/008 , B05C19/06 , B05D1/12 , B05D1/20 , B05D3/061 , B05D3/12 , B05D3/203
摘要： A facility for depositing a film of ordered particles onto a moving substrate, the facility configured to allow deposition, onto the substrate, of a film of ordered particles escaping from a particle outlet of a transfer zone having a first width. The facility further includes an accessory device in a form of a deposit head, provided to seal the particle outlet and configured to allow the deposition, onto the substrate, of a film of ordered particles escaping from an end of a particle transfer channel of the deposit head, the end having a second width strictly lower than the first width.
摘要翻译：一种用于将有序颗粒的膜沉积到移动的基底上的设施，该设备被配置为允许在基底上沉积从具有第一宽度的转移区的颗粒出口逸出的有序颗粒的膜。该设施还包括沉积头形式的附件装置，用于密封颗粒出口并且构造成允许在基板上沉积从沉积物的颗粒转移通道的端部排出的有序颗粒的膜头部，其端部具有严格低于第一宽度的第二宽度。

66. 发明授权

US08710494B2 Organic dual-gate memory and method for producing same 失效
标题翻译：有机双栅极存储器及其制造方法
公开(公告)号：US08710494B2
公开(公告)日：2014-04-29
申请号：US13500273
申请日：2010-09-30
申请人： Romain Gwoziecki , Mohamed Benwadih , Philippe Coronel , Stéphanie Jacob
发明人： Romain Gwoziecki , Mohamed Benwadih , Philippe Coronel , Stéphanie Jacob
IPC分类号： H01L21/02
CPC分类号： H01L51/0554 , H01L51/004 , H01L51/0516
摘要： The organic memory device is a double-gate transistor that successively comprises a first gate electrode, a first gate dielectric, an organic semi-conductor material, a second gate dielectric and a second gate electrode. Source and drain electrodes are arranged in the organic semiconductor material and define an inter-electrode surface. A trapping area is arranged between the organic semiconductor material and one of the gate electrodes and is in electric contact with one of the gate electrodes or the organic semi-conductor material. The trapping area is at least facing the inter-electrode surface.
摘要翻译：有机存储器件是双栅极晶体管，其连续地包括第一栅极电极，第一栅极电介质，有机半导体材料，第二栅极电介质和第二栅极电极。源电极和漏极布置在有机半导体材料中并限定电极间表面。在有机半导体材料和栅极电极之间布置有捕获区域，并且与栅极电极或有机半导体材料中的一个电接触。捕获区域至少面向电极间表面。

67. 发明申请

US20130330471A1 FACILITY AND METHOD FOR DEPOSITING A FILM OF ORDERED PARTICLES ONTO A MOVING SUBSTRATE 有权
标题翻译：将有序颗粒膜沉积在移动基板上的设施和方法
公开(公告)号：US20130330471A1
公开(公告)日：2013-12-12
申请号：US14001088
申请日：2012-02-20
申请人： Olivier Dellea , Pascal Fugier , Philippe Coronel
发明人： Olivier Dellea , Pascal Fugier , Philippe Coronel
IPC分类号： B05C19/02
CPC分类号： B05C19/02 , B05C19/00 , B05D1/00 , B05D1/20 , B05D1/204 , B05D2252/02
摘要： A facility for depositing a film of ordered particles onto a moving substrate, the facility including: a transfer area including an entry of particles and an exit of particles spaced apart from each other by two side edges facing each other, retaining a carrier liquid on which the particles float, a capillary bridge ensuring connection between the carrier liquid contained in the transfer area and the substrate, and a plurality of suction nozzles capable of attracting the particles towards its two side edges.
摘要翻译：一种用于将有序颗粒的膜沉积在移动的基底上的设备，该设备包括：传送区域，包括粒子的入口和通过彼此面对的两个侧边缘彼此间隔开的颗粒的出口，保持载体液体颗粒浮动，确保包含在传送区域中的载体液体与基板之间的连接的毛细管桥和能够将颗粒吸引到其两个侧边缘的多个吸嘴。

68. 发明申请

US20130052552A1 DEVICE FORMING A MANOMETER INTENDED FOR MEASURING BIPHASIC FLUID PRESSURE, ASSOCIATED METHOD OF MANUFACTURE AND FLUIDIC NETWORK 有权
标题翻译：设计用于测量双重流体压力的测力仪，相关的制造方法和流体网络
公开(公告)号：US20130052552A1
公开(公告)日：2013-02-28
申请号：US13642997
申请日：2011-04-27
申请人： Hai Trieu Phan , Philippe Coronel , Pascal Fugier , Jérôme Gavillet
发明人： Hai Trieu Phan , Philippe Coronel , Pascal Fugier , Jérôme Gavillet
IPC分类号： G01L7/18 , B81B1/00 , F28D21/00 , H01R43/00 , H01M8/06 , G01L9/00 , B23P17/00
CPC分类号： G01L7/18 , G01L9/0095 , Y10T29/49224 , Y10T29/494 , Y10T137/8326
摘要： A device forming a manometer, configured to measure pressure of a biphasic fluid in a fluidic network, including: a first channel inside which a biphasic fluid is able to flow; a second channel emerging into the first channel, wherein the second channel is blind, with each of its dimensions less than capillary length of the fluid's liquid phase, and with at least one of its lengthways wall having a surface energy gradient that decreases from its inlet to the end. The surface energy gradient enables the wetting angle of the meniscus of the fluid's liquid phase to be increased in the blind channel from its inlet to the end. Such a device may find application to measurement of pressure of a biphasic fluid in a heat exchanger or in a fuel cell.
摘要翻译：一种形成压力计的装置，被配置为测量流体网络中的双相流体的压力，包括：第一通道，双相流体能够在其中流动; 第二通道出现在第一通道中，其中第二通道是盲的，其每个尺寸小于流体的液相的毛细管长度，并且其长度壁中的至少一个具有从其入口减小的表面能量梯度到最后。表面能量梯度使得流体液相的弯液面的润湿角度在盲通道中从其入口到末端增加。这种装置可用于测量热交换器或燃料电池中双相流体的压力。

69. 发明申请

US20120070964A1 METHOD FOR ELIMINATING THE METAL CATALYST RESIDUES ON THE SURFACE OF WIRES PRODUCED BY CATALYTIC GROWTH 失效
标题翻译：用于消除催化生长线上金属催化剂残留物的方法
公开(公告)号：US20120070964A1
公开(公告)日：2012-03-22
申请号：US13220395
申请日：2011-08-29
申请人： Simon Perraud , Philippe Coronel
发明人： Simon Perraud , Philippe Coronel
IPC分类号： H01L21/20
CPC分类号： H01L29/0676 , B82Y40/00 , H01L21/0245 , H01L21/02463 , H01L21/02521 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02645 , H01L21/02664
摘要： This method for eliminating the catalyst residues present on the surface of solid structures made from a first material and obtained by catalytic growth, includes the following steps: catalytic growth, from the catalyst residues, of solid structures made from a second material; selective elimination of said solid structures made from a second material.
摘要翻译：用于消除由第一种材料制成并由催化生长获得的固体结构表面上存在的催化剂残余物的方法包括以下步骤：由第二种材料制成的固体结构从催化剂残余物中催化生长; 选择性地消除由第二材料制成的所述固体结构。

70. 发明授权

US07923315B2 Manufacturing method for planar independent-gate or gate-all-around transistors 有权
标题翻译：平面独立栅极或栅极全环晶体管的制造方法
公开(公告)号：US07923315B2
公开(公告)日：2011-04-12
申请号：US12809876
申请日：2008-12-18
申请人： Arnaud Pouydebasque , Philippe Coronel , Stephanne Denorme
发明人： Arnaud Pouydebasque , Philippe Coronel , Stephanne Denorme
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/42392 , H01L29/66484 , H01L29/66636 , H01L29/7831 , H01L29/78654
摘要： The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.
摘要翻译：本发明涉及一种在体半导体衬底上制造平面独立双栅极FET或平面栅极全周围FET的方法。该方法包括在有源半导体区域中用掩埋牺牲层重新填充表面凹槽，并且在通过相应的沉积和图案化准备预处理栅极堆叠之后，在隔离区域中形成凹槽，以便使凹部在指向内衬底的深度方向上延伸到允许去除掩埋牺牲层的深度水平，并且使得凹槽在通道方向上削弱栅极堆叠的部分。

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