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61. 发明授权

US07421643B2 Data detection and decoding system and a method of detecting and decoding data 失效
标题翻译：数据检测和解码系统以及数据检测和解码方法
公开(公告)号：US07421643B2
公开(公告)日：2008-09-02
申请号：US11029148
申请日：2005-01-04
申请人： Hongwei Song , German Feyh
发明人： Hongwei Song , German Feyh
IPC分类号： H03M13/00
CPC分类号： H04L1/0054 , H03M13/098 , H03M13/29 , H03M13/2909 , H03M13/2933 , H03M13/4146 , H03M13/6343 , H04L1/0063
摘要： A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.
摘要翻译：一种数据检测和解码系统，其中在信道检测器中使用由编码器添加到每个码字的末尾的单个奇偶校验位，以提高在信道检测器中进行位决定的精度。然后由解码器处理比特估计和可靠性估计以恢复原始输入比特。通过将这种双重目的的单一奇偶校验与跟随信道检测器的解码器结合使用，并使用比特估计和可靠性估计来恢复原始输入比特，数据检测和解码系统的性能大大提高，同时克服了已知的数字录音系统。

62. 发明申请

US20070192666A1 Systems and methods for error reduction associated with information transfer 有权
标题翻译：与信息传输相关的错误减少的系统和方法
公开(公告)号：US20070192666A1
公开(公告)日：2007-08-16
申请号：US11341963
申请日：2006-01-26
申请人： Hongwei Song , Weijun Tan
发明人： Hongwei Song , Weijun Tan
IPC分类号： H03M13/00
CPC分类号： H03M13/29 , G11B20/10296 , G11B20/1833 , G11B2020/1836 , H03M13/098 , H03M13/1515 , H03M13/3746 , H03M13/6331
摘要： Various systems and methods for error reduction in a digital information system are disclosed herein. As one example, a digital storage system is provided that includes a storage medium that with an encoded data set accessible via a buffer. The systems further include a soft output Viterbi algorithm channel detector operable to receive the encoded data set, and to provide a hard and a soft output representing the encoded data set. The hard and the soft output from the soft output Viterbi algorithm channel detector are provided to a single parity row decoder that provides another hard output that is an error reduced representation of the encoded data set. The encoded data set is additionally provided from the buffer to another channel detector via a delay element. The delay element time shifts the encoded data set to create a time shifted encoded data set. The hard output from the single parity row decoder and the time shifted encoded data set are provided to coincident with each other to another channel detector. This other channel detector provides a recovered output that exhibits a reduction in errors compared with the encoded data set.
摘要翻译：本文公开了用于数字信息系统中的差错减少的各种系统和方法。作为一个示例，提供数字存储系统，其包括具有经由缓冲器可访问的编码数据集的存储介质。所述系统还包括软输出维特比算法信道检测器，其可操作以接收编码数据集，并提供表示编码数据集的硬和软输出。来自软输出维特比算法信道检测器的硬和软输出被提供给单个奇偶校验行解码器，其提供作为编码数据集的错误减少表示的另一硬输出。编码数据集通过延迟元件从缓冲器附加地提供给另一个通道检测器。延迟元件时间移动编码数据集以创建时移编码数据集。提供来自单个奇偶校验行解码器和时移编码数据组的硬输出以彼此重合到另一个通道检测器。该另一通道检测器提供了与编码数据集相比显示出差错的恢复输出。

63. 发明申请

US20060168493A1 Data detection and decoding system and method 有权
标题翻译：数据检测与解码系统及方法
公开(公告)号：US20060168493A1
公开(公告)日：2006-07-27
申请号：US11041694
申请日：2005-01-24
申请人： Hongwei Song
发明人： Hongwei Song
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G11B20/1803 , G06F11/1008 , H03M13/41 , H03M13/4146 , H03M13/4153 , H03M13/6502
摘要： A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity. Because the SOVASP channel detector detects whether each code word satisfies single parity, it is unnecessary to use both a column decoder and a row decoder in the channel decoder. Either the row decoder or the column decoder can be eliminated depending on whether bits are read back on a column-by-column basis or on a row-by-row basis. This reduction in components reduces hardware complexity and improves system performance. The output of the row or column decoder is received by a second detector that processes the output received from the decoder to recover the original information bits.
摘要翻译：数据检测和解码系统包括使用单个奇偶校验（SOVASP）的SOVA信道检测器来提高检测器估计比特的精度。从读取通道读回的每个列或行构成一个代码字，每个代码字被编码以满足单个奇偶校验。因为SOVASP信道检测器检测每个码字是否满足单个奇偶校验，所以不必在信道解码器中使用列解码器和行解码器。取决于是逐列还是逐行读取位是否可以排除行解码器或列解码器。组件的这种减少降低了硬件复杂性并提高了系统性能。行或列解码器的输出由处理从解码器接收的输出的第二检测器接收以恢复原始信息位。

64. 发明授权

US10302133B2 Sealing structure for bearing 有权
公开(公告)号：US10302133B2
公开(公告)日：2019-05-28
申请号：US15747299
申请日：2016-06-01
申请人： Hongwei Song , Ling Nan , Fuqiang Cai , Uwe Niebling , Zhiheng Liu , Xin Liu
发明人： Hongwei Song , Ling Nan , Fuqiang Cai , Uwe Niebling , Zhiheng Liu , Xin Liu
IPC分类号： F16C33/78 , F16C33/80 , F16C19/36 , F16C19/38
摘要： Bearing sealing structures are disclosed, which may include first and second frameworks configured to attach to an outer ring and an inner ring, respectively, and an elastic sealing member. The first framework may include a first radially extending part extending towards the inner ring, the second framework may include a second radially extending part extending towards the outer ring, and the second radially extending part may be located on an axially outer side of the first radially extending part. The sealing structure may form a first chamber and a second chamber in a radial direction, the first chamber being formed by the first or second radially extending part. The second chamber may be located on a radially inner side of the first chamber, and the elastic sealing member may include a first sealing member extending into the first chamber and a second sealing member extending into the second chamber.

65. 发明授权

US08670955B2 Systems and methods for reliability assisted noise predictive filtering 有权
标题翻译：可靠性辅助噪声预测滤波的系统和方法
公开(公告)号：US08670955B2
公开(公告)日：2014-03-11
申请号：US13088178
申请日：2011-04-15
申请人： Lingyan Sun , Hongwei Song , Jingfeng Liu
发明人： Lingyan Sun , Hongwei Song , Jingfeng Liu
IPC分类号： G06F19/00 , G11B5/09
CPC分类号： G11B20/10287 , G11B20/10009 , G11B20/10296 , G11B20/10509
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a calibration circuit, and an enable circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output based at least in part on control values. The calibration circuit operable to update the control values based at least in part on the data input, the detected output, and a calibration circuit enable. The calibration circuit enable is generated by the enable circuit based at least in part on the detected output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括：数据检测器电路，校准电路和使能电路。数据检测器电路可操作以将数据检测算法应用于数据输入，以至少部分地基于控制值产生检测到的输出。校准电路可操作以至少部分地基于数据输入，检测到的输出和校准电路使能来更新控制值。校准电路使能由至少部分地基于所检测的输出的使能电路产生。

66. 发明授权

US08451158B2 Analog to digital converter with generalized beamformer 有权
标题翻译：具有广义波束形成器的模数转换器
公开(公告)号：US08451158B2
公开(公告)日：2013-05-28
申请号：US13174273
申请日：2011-06-30
申请人： Yu Liao , Hongwei Song
发明人： Yu Liao , Hongwei Song
IPC分类号： H03M1/12
CPC分类号： H03M1/0602 , H03M1/1215
摘要： Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.
摘要翻译：本发明的各种实施例提供了用于执行模数转换的系统，装置和方法。例如，讨论了包括模拟输入，多个模数转换器和广义波束形成器的模数转换器电路。模数转换器可操作以接收模拟输入并产生多个数字流。每个模数转换器对具有不同相位偏移的模拟输入进行采样。广义波束形成器可操作以加权并组合数字流以产生数字输出。

67. 发明申请

US20130097213A1 Nyquist Constrained Digital Finite Impulse Response Filter 有权
标题翻译：奈奎斯特约束数字有限脉冲响应滤波器
公开(公告)号：US20130097213A1
公开(公告)日：2013-04-18
申请号：US13272209
申请日：2011-10-12
申请人： Yu Liao , Hongwei Song , Jingfeng Liu , Haotian Zhang
发明人： Yu Liao , Hongwei Song , Jingfeng Liu , Haotian Zhang
IPC分类号： G06F17/10
CPC分类号： G06F17/15 , H03H17/06 , H03H2017/0222
摘要： Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.
摘要翻译：本发明的各种实施例提供了用奈奎斯特约束数字有限脉冲响应滤波器对数字信号进行滤波的装置和方法。例如，公开了一种用于对数字数据进行滤波的装置，其包括具有多个抽头的数字有限脉冲响应滤波器。该装置还包括连接到数字有限脉冲响应滤波器的抽头加权控制器，可操作以调整抽头子集中的每一个的抽头权重，使得数字有限脉冲响应滤波器的奈奎斯特响应的幅度保持在约束范围。

68. 发明授权

US08341495B2 Method for detecting short burst errors in LDPC system 有权
标题翻译：用于检测LDPC系统中短脉冲串错误的方法
公开(公告)号：US08341495B2
公开(公告)日：2012-12-25
申请号：US13469746
申请日：2012-05-11
申请人： Weijun Tan , Shaohua Yang , Hongwei Song
发明人： Weijun Tan , Shaohua Yang , Hongwei Song
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H03M13/1128 , H03M13/17
摘要： The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal via the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.
摘要翻译：本发明是用于检测短脉冲串错误的装置。该设备包括第一信号输入，其中第一信号输入被配置为接收第一信号。该设备包括第二信号输入，其中第二信号输入被配置为接收第二信号。该器件包括逻辑门，其中逻辑门可操作用于经由第一信号输入接收第一信号，经由第二信号输入接收第二信号，并且基于接收到的第一信号和第二信号产生逻辑输出门信号信号。此外，该器件包括滤波器，其中滤波器被配置为从逻辑门接收逻辑输出门信号，并且基于接收的逻辑输出门信号产生滤波器输出信号，其中滤波器输出信号可用于标记误差。

69. 发明申请

US20120158810A1 Systems and Methods for Reducing Filter Sensitivities 有权
标题翻译：减少过滤器灵敏度的系统和方法
公开(公告)号：US20120158810A1
公开(公告)日：2012-06-21
申请号：US12972942
申请日：2010-12-20
申请人： Yu Liao , Hongwei Song , Lingyan Sun
发明人： Yu Liao , Hongwei Song , Lingyan Sun
IPC分类号： G06F17/10
CPC分类号： H03H21/0012 , G11B20/10055 , G11B20/10462 , G11B2220/2516 , H03H21/0067
摘要： Various embodiments of the present invention provide systems and methods for reducing filter sensitivities. As an example, reduced sensitivity filter circuits are discussed that include a digital filter and a filter tap adaptation circuit. The digital filter is operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output. The filter tap adaptation circuit is operable to receive an error value and a weighting control value, and to adaptively calculate at least one of the filter taps using the error value and the weighting control value.
摘要翻译：本发明的各种实施例提供了用于降低过滤器灵敏度的系统和方法。作为示例，讨论了包括数字滤波器和滤波器抽头适配电路的降低灵敏度滤波器电路。数字滤波器可操作以至少部分地基于多个滤波器抽头对接收到的输入进行滤波，并提供滤波输出。滤波器抽头适配电路可操作以接收误差值和加权控制值，并且使用误差值和加权控制值自适应地计算滤波器抽头中的至少一个。

70. 发明授权

US08189728B1 Jitter measurement 有权
标题翻译：抖动测量
公开(公告)号：US08189728B1
公开(公告)日：2012-05-29
申请号：US13108151
申请日：2011-05-16
申请人： Jingfeng Liu , Hongwei Song
发明人： Jingfeng Liu , Hongwei Song
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： G11B20/1816 , G11B20/10009 , G11B20/10444 , G11B2220/2541 , G11B2220/2562
摘要： A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after.
摘要翻译：专门的结构通过使用过零点两侧的测量信号值平均二交叉零二值估计的结果来测量光存储器接口中的时钟到数据抖动。在一个实施例中，第一估计在过零之前使用两个采样点和一个采样点之后，而第二估计在过零点之前使用一个采样点，并且采样两点之后。

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