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61. 发明授权

US08341356B2 Protected cache architecture and secure programming paradigm to protect applications 有权
标题翻译：保护缓存架构和安全编程范例来保护应用程序
公开(公告)号：US08341356B2
公开(公告)日：2012-12-25
申请号：US13099479
申请日：2011-05-03
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/06
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/1491 , G06F21/10
摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。描述和要求保护其他实施例。

62. 发明授权

US07975129B2 Selective hardware lock disabling 有权
标题翻译：选择性硬件锁定禁用
公开(公告)号：US07975129B2
公开(公告)日：2011-07-05
申请号：US12562457
申请日：2009-09-18
申请人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
发明人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/526
摘要： Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
摘要翻译：描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。该设备可以基于窥探，选择性地中止与CS相关联的事务。

63. 发明授权

US07587584B2 Mechanism to exploit synchronization overhead to improve multithreaded performance 有权
标题翻译：利用同步开销来提高多线程性能的机制
公开(公告)号：US07587584B2
公开(公告)日：2009-09-08
申请号：US11070991
申请日：2005-03-02
申请人： Natalie D. Enright , Jamison D. Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
发明人： Natalie D. Enright , Jamison D. Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/4843 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchronization object. The event detector can cause a first thread switch in response to the long latency event associated with the synchronization object. The apparatus may also include a spin detector to detect that the synchronization object is a contended synchronization object. The spin detector can cause a second thread switch in response to the detection of the contended synchronization object to enable a spin detect response.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。在一个实施例中，装置包括执行多个指令的执行资源和用于检测与同步对象相关联的长延迟事件的事件检测器。事件检测器可以响应于与同步对象相关联的长等待时间事件而导致第一线程切换。该装置还可以包括检测同步对象是竞争同步对象的自旋检测器。响应于竞争的同步对象的检测，自旋检测器可以引起第二线程切换以启用自旋检测响应。

64. 发明申请

US20090070774A1 LIVE LOCK FREE PRIORITY SCHEME FOR MEMORY TRANSACTIONS IN TRANSACTIONAL MEMORY 有权
标题翻译：实时锁定用于存储器交易的优先存储器
公开(公告)号：US20090070774A1
公开(公告)日：2009-03-12
申请号：US11854175
申请日：2007-09-12
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F9/46
CPC分类号： G06F9/524 , G06F9/466
摘要： A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
摘要翻译：这里描述了用于在事务执行期间避免实时锁定的方法和装置。计数逻辑用于跟踪每个处理元素的成功提交事务。当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

65. 发明授权

US07454601B2 N-wide add-compare-select instruction 有权
标题翻译： N宽加比选择指令
公开(公告)号：US07454601B2
公开(公告)日：2008-11-18
申请号：US10107259
申请日：2002-03-28
申请人： Gad Sheaffer
发明人： Gad Sheaffer
IPC分类号： G06F9/315 , G06F9/42 , H03M13/41
CPC分类号： G06F9/30014 , G06F9/30021 , G06F9/30094
摘要： The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and selecting a plurality of branch metrics. The method also includes combining the plurality of branch metrics with a plurality of source operands and outputting a pair of maximum values.
摘要翻译：本发明涉及一种用于提供N宽加法比较选择指令的方法和系统，包括将指令解码为N宽加法比较选择指令并选择多个分支度量。该方法还包括将多个分支度量与多个源操作数组合并输出一对最大值。

66. 发明申请

US20070124736A1 Acceleration threads on idle OS-visible thread execution units 有权
标题翻译：空闲OS可见线程执行单元上的加速线程
公开(公告)号：US20070124736A1
公开(公告)日：2007-05-31
申请号：US11288823
申请日：2005-11-28
申请人： Ron Gabor , Gad Sheaffer , Avi Mendelson , Uri Weiser , Hong Wang
发明人： Ron Gabor , Gad Sheaffer , Avi Mendelson , Uri Weiser , Hong Wang
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/5027 , G06F2209/5018
摘要： Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non- idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.
摘要翻译：公开了使用空闲螺纹单元执行对操作系统透明的加速度线程的系统，方法和机构的实施例。当操作系统调度器没有在空闲线程单元上进行调度时，操作系统可以发出停止或监视/等待或其他指令来将线程单元置于空闲状态。当螺纹单元处于空闲状态时，从操作系统的角度来看，螺纹单元可用于执行推测加速螺纹，以加速在非空转螺纹单元上运行的螺纹。在执行加速线程之前保存空闲线程单元的上下文，并且当操作系统需要使用线程单元时被恢复。加速线程对操作系统是透明的。还描述和要求保护其他实施例。

67. 发明授权

US07028171B2 Multi-way select instructions using accumulated condition codes 失效
标题翻译：使用累积条件代码的多路选择指令
公开(公告)号：US07028171B2
公开(公告)日：2006-04-11
申请号：US10107266
申请日：2002-03-28
申请人： Gad Sheaffer
发明人： Gad Sheaffer
IPC分类号： G06F9/40
CPC分类号： G06F9/30094 , G06F9/30061 , G06F9/30181 , G06F9/3842
摘要： The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.
摘要翻译：本发明涉及一种在处理器中提供N路选择指令的方法和系统。具体地，提供N路选择指令的方法包括将指令解码为N路选择指令。该方法还包括使用来自多个并行控制寄存器的信息从多个指令操作数中选择至少一对源操作数。所述方法还包括从所选择的至少一对源操作数中的每一个选择最终源操作数，并输出所选择的最终源操作数中的每一个。一般来说，任何N路选择指令都将具有M =对数2级的运行阶段。

68. 发明授权

US09003421B2 Acceleration threads on idle OS-visible thread execution units 有权
标题翻译：空闲OS可见线程执行单元上的加速线程
公开(公告)号：US09003421B2
公开(公告)日：2015-04-07
申请号：US11288823
申请日：2005-11-28
申请人： Ron Gabor , Gad Sheaffer , Avi Mendelson , Uri C. Weiser , Hong Wang
发明人： Ron Gabor , Gad Sheaffer , Avi Mendelson , Uri C. Weiser , Hong Wang
IPC分类号： G06F9/46 , G06F9/30 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/5027 , G06F2209/5018
摘要： Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.
摘要翻译：公开了使用空闲螺纹单元执行对操作系统透明的加速度线程的系统，方法和机构的实施例。当操作系统调度器没有在空闲线程单元上进行调度时，操作系统可以发出停止或监视/等待或其他指令来将线程单元置于空闲状态。当线程单元处于空闲状态时，从操作系统的角度来看，线程单元可用于执行推测加速线程，以加速在非空闲线程单元上运行的线程。空闲线程单元的上下文在执行加速线程之前被保存，并且当操作系统需要使用线程单元时被恢复。加速线程对操作系统是透明的。还描述和要求保护其他实施例。

69. 发明申请

US20130301516A1 DIGITAL RELAY FOR OUT OF NETWORK DEVICES 有权
标题翻译：用于网络设备的数字继电器
公开(公告)号：US20130301516A1
公开(公告)日：2013-11-14
申请号：US13817926
申请日：2012-05-09
申请人： Shmuel Ur , Gad Sheaffer
发明人： Shmuel Ur , Gad Sheaffer
IPC分类号： H04W76/02
CPC分类号： H04W76/02 , H04W76/10 , H04W88/04
摘要： In one example of digital relay for out of network devices, a communications device includes a detecting component configured to detect that one or more communication endpoints is within communication range, a message receiving component configured to receive a digital message from a first communication endpoint, and a message relaying component configured to transmit the digital message to the second communication endpoint, wherein the first communication endpoint and the second communication endpoint are not communicatively coupled to each other.
摘要翻译：在网络设备的数字中继的一个示例中，通信设备包括被配置为检测一个或多个通信端点在通信范围内的检测组件，被配置为从第一通信端点接收数字消息的消息接收组件，以及消息中继组件，被配置为将数字消息发送到第二通信端点，其中第一通信端点和第二通信端点不通信地彼此耦合。

70. 发明申请

US20090172304A1 Obscuring Memory Access Patterns in Conjunction with Deadlock Detection or Avoidance 有权
标题翻译：阻止内存访问模式与死锁检测或避免相关联
公开(公告)号：US20090172304A1
公开(公告)日：2009-07-02
申请号：US11966794
申请日：2007-12-28
申请人： Shay Gueron , Gad Sheaffer , Shlomo Raikin
发明人： Shay Gueron , Gad Sheaffer , Shlomo Raikin
IPC分类号： G06F12/00
CPC分类号： G06F12/0808 , G06F12/0802 , G06F21/556 , G06F2201/885 , G06F2212/1052 , H04L9/003
摘要： Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
摘要翻译：提供了存储器访问遮蔽的方法，装置和系统。第一实施例提供结合死锁避免的存储器访问遮蔽。这种实施例利用处理器特征，包括能够监视指定的高速缓存行的指令，以及响应于指定行的任何外部访问（例如，由于读取的写入或驱逐）而设置状态位的指令。第二实施例提供结合死锁检测的存储器访问遮蔽。这种实施例利用监视特征以及处理程序注册。响应于对任何指定行的外部写入，可以异步调用用户级处理程序。调用处理程序比预期更频繁表示可能遇到死锁。在这种情况下，可能会执行死锁策略。还描述和要求保护其他实施例。

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