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61. 发明授权

US08736019B2 Semiconductor devices with sealed, unlined trenches and methods of forming same 有权
公开(公告)号：US08736019B2
公开(公告)日：2014-05-27
申请号：US13091410
申请日：2011-04-21
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L21/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.

62. 发明申请

US20130049107A1 TRENCH SEMICONDUCTOR POWER DEVICE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： TRENCH SEMICONDUCTOR POWER DEVICE及其制造方法
公开(公告)号：US20130049107A1
公开(公告)日：2013-02-28
申请号：US13576702
申请日：2010-06-29
申请人： Koon Chong So
发明人： Koon Chong So
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/407 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A trench semiconductor power device and a fabrication method. The fabrication method includes: eroding an n epitaxial layer on an n+ substrate to form multiple gate trenches, and implanting with dopants to form source regions and P type base regions, respectively; eroding an interlayer dielectric to form a trench plug; and eroding an aluminum copper alloy to form a metal pad layer and wires. The method forms the source regions and the base regions by directly implanting, does not need source region masks and base region masks, has a simple fabrication process, and improves the quality and reliability of the device.
摘要翻译：沟槽半导体功率器件及其制造方法。该制造方法包括：蚀刻n +衬底上的n外延层以形成多个栅极沟槽，并用掺杂剂注入以分别形成源极区域和P型基极区域; 腐蚀层间电介质以形成沟槽塞; 并腐蚀铝铜合金以形成金属焊盘层和电线。该方法通过直接注入形成源区和基区，不需要源区掩模和基区掩模，具有简单的制造工艺，提高了器件的质量和可靠性。

63. 发明申请

US20110193176A1 Semiconductor Devices with Sealed, Unlined Trenches and Methods of Forming Same 有权
标题翻译：具有密封，无衬底的沟槽的半导体器件及其形成方法
公开(公告)号：US20110193176A1
公开(公告)日：2011-08-11
申请号：US13091410
申请日：2011-04-21
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L27/06 , H01L29/06
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

64. 发明授权

US5998266A Method of forming a semiconductor structure having laterally merged body layer 失效
标题翻译：形成具有横向合并体层的半导体结构的方法
公开(公告)号：US5998266A
公开(公告)日：1999-12-07
申请号：US781934
申请日：1996-12-19
申请人： Koon Chong So
发明人： Koon Chong So
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696
摘要： A trenched gate MOSFET (metal oxide semiconductor field effect transistor) structure is fabricated via a novel process which includes the step of using a common mask serving the dual role as a mask for the body layer formation and as a mask for trench etching. The common mask defines an patterned oxide layer which includes a plurality of openings at a predetermined distance away from the scribe line of the MOSFET structure. During fabrication, material of the body layer is implanted through the openings of the patterned oxide layer. Thereafter, the implanted material is side-diffused and merged together under a drive-in cycle as one continuous body layer. Using the same patterned oxide layer as a shield, trenches are anisotropically etched in the substrate. The MOSFET structure as formed requires no separate mask for delineating the active body region away from the scribe line, resulting reduction of fabrication steps. The consequential benefits are lower manufacturing costs and higher production yields.
摘要翻译：沟槽栅极MOSFET（金属氧化物半导体场效应晶体管）结构通过一种新颖的工艺制造，该方法包括使用兼作双重作用的共同掩模作为体层形成的掩模和用于沟槽蚀刻的掩模的步骤。公共掩模限定图案化氧化物层，其包括离开MOSFET结构的划线一预定距离的多个开口。在制造期间，通过图案化氧化物层的开口注入体层的材料。此后，植入材料在作为一个连续体层的驱入周期中侧向扩散并且合并在一起。使用相同的图案化氧化物层作为屏蔽，在衬底中各向异性蚀刻沟槽。形成的MOSFET结构不需要用于将活性物体区域划分成远离划线的单独的掩模，从而减少制造步骤。相应的好处是降低制造成本和提高产量。

65. 发明授权

US08716829B2 Semiconductor devices with sealed, unlined trenches and methods of forming same 有权
标题翻译：具有密封，无衬里的沟槽的半导体器件及其形成方法
公开(公告)号：US08716829B2
公开(公告)日：2014-05-06
申请号：US13091416
申请日：2011-04-21
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L21/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

66. 发明授权

US08129252B2 Semiconductor devices with sealed, unlined trenches and methods of forming same 有权
标题翻译：具有密封，无衬里的沟槽的半导体器件及其形成方法
公开(公告)号：US08129252B2
公开(公告)日：2012-03-06
申请号：US12472424
申请日：2009-05-27
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L21/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

67. 发明授权

US07944018B2 Semiconductor devices with sealed, unlined trenches and methods of forming same 有权
标题翻译：具有密封，无衬里的沟槽的半导体器件及其形成方法
公开(公告)号：US07944018B2
公开(公告)日：2011-05-17
申请号：US11838359
申请日：2007-08-14
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L21/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

68. 发明授权

US5763915A DMOS transistors having trenched gate oxide 失效
标题翻译：具有沟槽栅极氧化物的DMOS晶体管
公开(公告)号：US5763915A
公开(公告)日：1998-06-09
申请号：US607715
申请日：1996-02-27
申请人： Fwu-Juan Hshieh , True-Lon Lin , Danny Chi Nim , Koon Chong So , Yan Man Tsui
发明人： Fwu-Juan Hshieh , True-Lon Lin , Danny Chi Nim , Koon Chong So , Yan Man Tsui
IPC分类号： H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42372 , H01L29/66734 , H01L29/7811 , H01L29/0619 , H01L29/0638 , H01L29/402 , H01L29/4238
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve cost savings by simplified device structure and fabrication processes, and also by reducing the required die size. Specifically, in a novel MOSFET device, insulation of mobile ions are achieved by extending the poly gate and metal contacts such that the passivation layer is no longer required and the fabrication process is simplified such that the MOSFET device can be manufactured at a lower price. Furthermore, in another MOSFET device, the gate runner is used to replace the field plate such that the requirement of a field plate as that in a conventional MOSFET device is also eliminated and, by reducing the die size, the cost of manufacture is further reduced.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺，以通过简化的器件结构和制造工艺以及通过减少所需的管芯尺寸来实现成本节约。具体地说，在新颖的MOSFET器件中，通过延长多晶硅栅极和金属触点来实现移动离子的绝缘，从而不再需要钝化层，并且简化了制造工艺，使得可以以更低的价格制造MOSFET器件。此外，在另一个MOSFET器件中，栅极流道用于替代现场板，使得现场板的需求与常规MOSFET器件中的要求也被消除，并且通过减小管芯尺寸，制造成本进一步降低。

69. 发明申请

US20090233415A1 Semiconductor Devices with Sealed, Unlined Trenches and Methods of Forming Same 有权
标题翻译：具有密封，无衬底的沟槽的半导体器件及其形成方法
公开(公告)号：US20090233415A1
公开(公告)日：2009-09-17
申请号：US12472424
申请日：2009-05-27
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L21/764
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

70. 发明申请

US20110193158A1 Semiconductor Devices With Sealed, Unlined Trenches and Methods of Forming Same 有权
标题翻译：具有密封，无衬底的沟槽和形成方法的半导体器件
公开(公告)号：US20110193158A1
公开(公告)日：2011-08-11
申请号：US13091416
申请日：2011-04-21
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

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