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61. 发明授权

US5500557A Structure and method for fabricating integrated circuits 失效
标题翻译：集成电路制造的结构和方法
公开(公告)号：US5500557A
公开(公告)日：1996-03-19
申请号：US126673
申请日：1993-09-24
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后在集成电路上形成绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

62. 发明授权

US5478771A Method of forming local interconnect structure without P-N junction between active elements 失效
标题翻译：在有源元件之间形成不具有P-N结的局部互连结构的方法
公开(公告)号：US5478771A
公开(公告)日：1995-12-26
申请号：US359006
申请日：1994-12-19
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L21/70
CPC分类号： H01L23/53271 , H01L21/76889 , H01L21/76895 , H01L27/1104 , H01L2924/0002 , Y10S148/039 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

63. 发明授权

US5250456A Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby 失效
标题翻译：形成集成电路电容器电介质的方法和由此形成的电容器
公开(公告)号：US5250456A
公开(公告)日：1993-10-05
申请号：US759465
申请日：1991-09-13
申请人： Frank R. Bryant
发明人： Frank R. Bryant
IPC分类号： H01L21/265 , H01L21/314 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/00 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L21/3144 , H01L27/10808
摘要： A method of forming a capacitor in an integrated circuit, such as a dynamic random access memory (DRAM), and a capacitor and DRAM cell formed by such a method, is disclosed. A first capacitor plate is formed of silicon, for example polysilicon, followed by oxidation thereof to form a thin capacitor oxide layer thereover; alternatively, the thin capacitor oxide layer may be deposited. Nitrogen ions are then implanted through the oxide and into the silicon. A high temperature anneal is then performed in a nitrogen atmosphere, which causes the implanted nitrogen to accumulate near the interface between the silicon first plate and the oxide layer, forming a nitride-like region thereat. An optional sealing thermal reaction (oxidation or nitridation) may then be performed, to reduce the effects of pinholes or other defects in the composite film. The second plate may then be formed of polysilicon, metal, or a metal silicide, completing the capacitor.

64. 发明授权

US5231043A Contact alignment for integrated circuits 失效
标题翻译：集成电路接点对齐
公开(公告)号：US5231043A
公开(公告)日：1993-07-27
申请号：US748085
申请日：1991-08-21
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/76802 , H01L27/10805
摘要： A technique for producing self-aligned contact openings is especially useful when the openings are to be made between conductive structures having relatively small separation. Formation of an oxide layer under particular process conditions results in a thicker layer of oxide on top of the conductive structures, and a thinner oxide layer along the sidewalls and in the bottom of the spacing between them. Deposition of such a differential thickness oxide layer can be followed by an unmasked-anisotropic etch in order to clear the oxide from the space between the conductive structures, without removing all of the oxide layer over the conductive structure. Such a technique can be utilized in integrated circuits such as DRAMs, with the word lines allowing for the formation of semi-self-aligned bit lines. The combination of word lines and bit lines can provide for a fully self-aligned contact opening for DRAM cell capacitors.

65. 发明授权

US5204279A Method of making SRAM cell and structure with polycrystalline p-channel load devices 失效
标题翻译：制造具有多晶p沟道负载器件的SRAM单元和结构的方法
公开(公告)号：US5204279A
公开(公告)日：1993-04-20
申请号：US709354
申请日：1991-06-03
申请人： Tsiu C. Chan , Frank R. Bryant , Lisa K. Jorgenson
发明人： Tsiu C. Chan , Frank R. Bryant , Lisa K. Jorgenson
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices. A second insulating layer is formed over the integrated circuit having an opening exposing a portion of the interconnect layer. A first conductive layer is formed over the integrated circuit, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A gate oxide layer is formed over a portion of the first gate electrode and a portion of the second gate electrode of the first and second P-channel devices. A second conductive layer is formed over the integrated circuit, patterned and etched to define a source/drain and channel region of the first gate electrode of the first P-channel device and covering a portion of the second gate electrode of the second P-channel device.
摘要翻译：公开了一种用于形成具有集成电路的多晶P沟道负载装置的SRAM结构的方法，以及根据该集成电路形成的集成电路。在衬底的一部分上形成场氧化物区域。在衬底上形成第一N沟道场效应器件的第一栅电极，该衬底上具有衬底中的源/漏区。第二N沟道场效应器件的第二栅电极也形成在衬底和场氧化物的一部分上。在集成电路上形成第一绝缘层，该集成电路包含分别露出第一和第二N沟道器件的源极/漏极区域和第二栅极电极的一部分的开口。在集成电路上形成具有掺杂多晶硅层和阻挡层的互连层，被图案化和蚀刻以限定覆盖N沟道器件的暴露的源极/漏极区域和第二栅极电极的共享接触区域。在集成电路上形成第二绝缘层，该绝缘层具有露出互连层的一部分的开口。在集成电路上形成第一导电层，被图案化和蚀刻以分别限定第一和第二P沟道场效应器件的第一和第二栅电极。在第一栅电极的一部分和第一和第二P沟道器件的第二栅电极的一部分上形成栅氧化层。在集成电路上形成第二导电层，被图案化和蚀刻以限定第一P沟道器件的第一栅电极的源极/漏极和沟道区，并且覆盖第二P沟道的第二栅电极的一部分设备。

66. 发明授权

US5187114A Method of making SRAM cell and structure with polycrystalline P-channel load devices 失效
标题翻译：制造具有多晶P沟道负载器件的SRAM单元和结构的方法
公开(公告)号：US5187114A
公开(公告)日：1993-02-16
申请号：US709630
申请日：1991-06-03
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1108
摘要： A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of a field oxide. A metal containing layer is formed over the second gate electrode and the source/drain region of the first N-channel device to define a shared contact region. A first conductive layer is formed over the metal containing layer, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A second conductive layer is formed over a portion of the first and second P-channel devices, to define a source/drain and channel region of the P-channel devices.
摘要翻译：公开了一种用于形成具有集成电路的多晶P沟道负载装置的SRAM结构的方法，以及根据该集成电路形成的集成电路。在衬底上形成第一N沟道场效应器件的第一栅电极，该衬底上具有衬底中的源/漏区。第二N沟道场效应器件的第二栅电极也形成在衬底和场氧化物的一部分上。金属含有层形成在第一N沟道器件的第二栅极电极和源极/漏极区域上，以限定共享接触区域。第一导电层形成在含金属层之上，被图案化和蚀刻以分别限定第一和第二P沟道场效应器件的第一和第二栅电极。在第一和第二P沟道器件的一部分上形成第二导电层，以限定P沟道器件的源极/漏极和沟道区。

67. 发明授权

US5116776A Method of making a stacked copacitor for DRAM cell 失效
标题翻译：制造用于DRAM单元的堆叠复合体的方法
公开(公告)号：US5116776A
公开(公告)日：1992-05-26
申请号：US443897
申请日：1989-11-30
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10817 , H01L28/40 , Y10S438/954
摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.
摘要翻译：适用于DRAM存储单元的电容器由多层多晶硅组成。存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

68. 发明授权

US4863562A Method for forming a non-planar structure on the surface of a semiconductor substrate 失效
标题翻译：在半导体衬底的表面上形成非平面结构的方法
公开(公告)号：US4863562A
公开(公告)日：1989-09-05
申请号：US155148
申请日：1988-02-11
申请人： Frank R. Bryant , Fu-Tai Liou
发明人： Frank R. Bryant , Fu-Tai Liou
IPC分类号： H01L21/32 , H01L21/336 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202 , H01L29/66795
摘要： A method for increasing the width of a transistor includes first forming a nitride cap (14) over the substrate (10) and then forming trenches (24) and (26) on either side of the cap (14) and having tapered sidewalls (28) and (30). A conformal layer of nitride (32) is formed over the substrate and then anisotropically etched to form sidewall layers (34) and (36). Field oxide is grown in the trenches with birds beaks (42) and (44) extending upward under the sidewall layers (34) and (36). A portion of the sidewalls (28) and (30) of the trenches remain such that the overall surface area between the edges of the birds beaks (42) and (44) is increased. A layer of strip oxide is then grown on the substrate to provide rounded edges (47) and (49). The strip oxide is then removed by a fifty percent over etch to cause the birds beaks (42) and (44) to recede, thus further increasing the surface area. The gate electrode of a transistor (54) can then be disposed thereacross, thus increasing the width of the transistor for a given silicon surface area in the initial material.

69. 发明授权

US4508815A Recessed metallization 失效
标题翻译：嵌入金属化
公开(公告)号：US4508815A
公开(公告)日：1985-04-02
申请号：US548465
申请日：1983-11-03
申请人： Paul W. Ackmann , Frank R. Bryant
发明人： Paul W. Ackmann , Frank R. Bryant
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/312 , H01L21/283
CPC分类号： H01L21/32137 , H01L21/32136 , H01L21/7688
摘要： An improved method of planarizing a level of metallization employs a trench in a smooth-surfaced dielectric and a sequence of etching steps to cut the trench locally down to the substrate, while forming the main metallization pattern at the same time.
摘要翻译：平坦化金属化水平的改进方法使用光滑表面电介质中的沟槽和一系列蚀刻步骤，以同时将沟槽局部切割到衬底，同时同时形成主金属化图案。

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