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61. 发明授权

US07411272B2 Semiconductor device and method of forming a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07411272B2
公开(公告)日：2008-08-12
申请号：US11174605
申请日：2005-07-06
申请人： Florin Udrea , Gehan A. J. Amaratunga
发明人： Florin Udrea , Gehan A. J. Amaratunga
IPC分类号： H01L29/00
CPC分类号： H01L29/7816 , H01L21/76289 , H01L21/764 , H01L29/0619 , H01L29/0634 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/083 , H01L29/1608 , H01L29/2003 , H01L29/42368 , H01L29/66325 , H01L29/66333 , H01L29/66348 , H01L29/7393 , H01L29/7394 , H01L29/7395 , H01L29/7397 , H01L29/7801 , H01L29/7802 , H01L29/7812 , H01L29/7813 , H01L29/7824 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.
摘要翻译：功率半导体器件具有包括漂移区域的有源区域。漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

62. 发明申请

US20060049406A1 Power semiconductor and method of fabrication 有权
公开(公告)号：US20060049406A1
公开(公告)日：2006-03-09
申请号：US10936721
申请日：2004-09-09
申请人： Gehan Amaratunga , Florin Udrea
发明人： Gehan Amaratunga , Florin Udrea
IPC分类号： H01L29/76
CPC分类号： H01L29/7824 , H01L21/84 , H01L27/1203 , H01L29/41725 , H01L29/4175 , H01L29/42368 , H01L29/78603 , H01L29/78624
摘要： This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.

63. 发明申请

US20050242369A1 Semiconductor device and method of forming a semiconductor device 有权
公开(公告)号：US20050242369A1
公开(公告)日：2005-11-03
申请号：US11174606
申请日：2005-07-06
申请人： Florin Udrea , Gehan Amaratunga
发明人： Florin Udrea , Gehan Amaratunga
IPC分类号： H01L21/329 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/12 , H01L29/20 , H01L29/24 , H01L29/32 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7816 , H01L21/76289 , H01L21/764 , H01L29/0619 , H01L29/0634 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/083 , H01L29/1608 , H01L29/2003 , H01L29/42368 , H01L29/66325 , H01L29/66333 , H01L29/66348 , H01L29/7393 , H01L29/7394 , H01L29/7395 , H01L29/7397 , H01L29/7801 , H01L29/7802 , H01L29/7812 , H01L29/7813 , H01L29/7824 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

64. 发明申请

US20050242368A1 Semiconductor device and method of forming a semiconductor device 有权
公开(公告)号：US20050242368A1
公开(公告)日：2005-11-03
申请号：US11174605
申请日：2005-07-06
申请人： Florin Udrea , Gehan Amaratunga
发明人： Florin Udrea , Gehan Amaratunga
IPC分类号： H01L21/329 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/12 , H01L29/20 , H01L29/24 , H01L29/32 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7816 , H01L21/76289 , H01L21/764 , H01L29/0619 , H01L29/0634 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/083 , H01L29/1608 , H01L29/2003 , H01L29/42368 , H01L29/66325 , H01L29/66333 , H01L29/66348 , H01L29/7393 , H01L29/7394 , H01L29/7395 , H01L29/7397 , H01L29/7801 , H01L29/7802 , H01L29/7812 , H01L29/7813 , H01L29/7824 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

65. 发明授权

US06259134B1 Trench thyristor with improved breakdown voltage characteristics 失效
标题翻译：具有改善击穿电压特性的沟槽晶闸管
公开(公告)号：US06259134B1
公开(公告)日：2001-07-10
申请号：US09112978
申请日：1998-07-09
申请人： Gehan A. J Amaratunga , Florin Udrea
发明人： Gehan A. J Amaratunga , Florin Udrea
IPC分类号： H01L2976
CPC分类号： H01L29/749 , H01L27/0716 , H01L29/42308 , H01L29/7455
摘要： A MOS-controllable power semiconductor trench device has a gate in the form of a trench which extends through a region of p type silicon into an n type region of low conductivity. A discontinous buried p layer below the bottom of the trench forms part of a thyristor which in operation is triggered into conduction by conduction of a PIN diode which is produced when an accumulation layer is formed in the n type region adjacent to the trench under the action of an on-state gate signal. The device has a high on-state conductivity and is protected against high voltage breakdown in its off-state by the presence of the buried layer. An off-state gate signal causes removal of the accumulation layer and conduction of the PIN diode and the thyristor ceases in safe, reliable and rapid manner.
摘要翻译： MOS可控功率半导体沟槽器件具有沟槽形式的栅极，其延伸穿过p型硅的区域到n型低导电区域。在沟槽底部下方的不连续埋层p层形成晶闸管的一部分，晶闸管在工作中通过PIN二极管的导通而被触发导通，该PIN二极管是当在作用下邻近沟槽的n型区域中形成蓄积层时产生的的状态门信号。器件具有高的导通状态，并且通过存在掩埋层来保护其处于其断开状态的高压击穿。截止状态的栅极信号使安全，可靠和快速地停止积聚层，PIN二极管和晶闸管的导通停止。

66. 发明授权

US6111289A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US6111289A
公开(公告)日：2000-08-29
申请号：US289615
申请日：1999-04-12
申请人： Florin Udrea
发明人： Florin Udrea
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/861 , H01L29/772
CPC分类号： H01L29/861 , H01L29/0634 , H01L29/7393 , H01L29/7394 , H01L29/7816 , H01L29/7824 , H01L29/41758
摘要： A semiconductor device has first and second electrical terminals. The device comprises at least one n/p or p/n first junction adjacent the first terminal, and at least one of the other of a p/n or n/p second junction adjacent the second terminal. It also has at least one n/p or p/n junction disposed between the first and second junctions and arranged to be transverse thereto, and at least one gate terminal in contact with the p or n doped region of the first junction or the n or p doped region of the second junction.
摘要翻译：半导体器件具有第一和第二电端子。该装置包括与第一端子相邻的至少一个n / p或p / n第一结，以及与第二端子相邻的p / n或n / p第二接头中的至少一个。它还具有至少一个n / p或p / n结，该n / p或p / n结设置在第一和第二结之间并且布置成横向于其，并且至少一个栅极端子与第一结的p或n掺杂区域或n 或第二结的p掺杂区域。

67. 发明授权

US08866252B2 Power semiconductor devices and fabrication methods 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08866252B2
公开(公告)日：2014-10-21
申请号：US13233672
申请日：2011-09-15
申请人： Tanya Trajkovic , Florin Udrea , Vasantha Pathirana , Nishad Udugampola
发明人： Tanya Trajkovic , Florin Udrea , Vasantha Pathirana , Nishad Udugampola
IPC分类号： H01L23/58 , H01L29/66 , H01L29/78 , H01L29/739 , H01L29/10 , H01L29/06 , H01L29/423
CPC分类号： H01L29/0634 , H01L29/1033 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/66325 , H01L29/66681 , H01L29/7393 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.
摘要翻译：我们描述了具有p顶层的n-漂移区的RESURF半导体器件，并且其中在该p顶层中形成该器件的MOS（金属氧化物半导体）沟道。

68. 发明申请

US20130320511A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130320511A1
公开(公告)日：2013-12-05
申请号：US13486614
申请日：2012-06-01
申请人： Elizabeth Kho Ching Tee , Alexander Dietrich Hölke , Steven John Pilkington , Deb Kumar Pal , Marina Antoniou , Florin Udrea
发明人： Elizabeth Kho Ching Tee , Alexander Dietrich Hölke , Steven John Pilkington , Deb Kumar Pal , Marina Antoniou , Florin Udrea
IPC分类号： H01L29/02
CPC分类号： H01L29/402 , H01L21/761 , H01L29/0634 , H01L29/0692 , H01L29/404 , H01L29/7823 , H01L29/861
摘要： A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.
摘要翻译：一种包括p或p +掺杂部分和通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分的半导体器件。该装置还包括邻近漂移部分设置的至少一个终端部分。所述至少一个终端部分包括超结结构。

69. 发明授权

US08482031B2 Lateral insulated gate bipolar transistors (LIGBTS) 失效
标题翻译：横向绝缘栅双极晶体管（LIGBTS）
公开(公告)号：US08482031B2
公开(公告)日：2013-07-09
申请号：US12648818
申请日：2009-12-29
申请人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
发明人： Florin Udrea , Vasantha Pathirana , Tanya Trajkovic , Nishad Udugampola
IPC分类号： H01L29/739 , H01L21/761 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/66325 , H01L29/7393
摘要： This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv
摘要翻译：本发明一般涉及横向绝缘栅双极晶体管（LIGBT），例如在集成电路中，提高LIGBT的开关速度的方法，抑制体硅LIGBT中的寄生晶闸管闩锁的方法以及制造LIGBT的方法。特别地，抑制体硅LIGBT中的寄生晶闸管闩锁的方法包括为LIGBT的寄生晶闸管的垂直晶体管选择电流增益α，使得在LIGBT的至少一个预定操作模式中，alphav <1 其中alphap是具有由半导体表面和富含金属的环氧树脂裸片附着之间的肖特基接触形成的基极 - 发射极的寄生双极晶体管的电流增益。

70. 发明授权

US08053783B2 Switching device 失效
标题翻译：开关装置
公开(公告)号：US08053783B2
公开(公告)日：2011-11-08
申请号：US11575114
申请日：2005-09-08
申请人： Gehan Anil Joseph Amaratunga , Mihai Brezeanu , Jeremy Suhail Rashid , Nalin Lalith Rupesinghe , Antonella Tajani , Daniel James Twitchen , Florin Udrea , Christopher John Howard Wort
发明人： Gehan Anil Joseph Amaratunga , Mihai Brezeanu , Jeremy Suhail Rashid , Nalin Lalith Rupesinghe , Antonella Tajani , Daniel James Twitchen , Florin Udrea , Christopher John Howard Wort
IPC分类号： H01L31/10 , H01J47/00
CPC分类号： H01L31/108 , H01L31/028 , H01L31/0288 , H01L31/118 , Y02E10/547
摘要： A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux, and capable of being switched off in the presence of the high voltage being switched. The device includes a diamond body having a Schottky barrier contact, held in reverse bias by the applied voltage to be switched, to an essentially intrinsic diamond layer or portion in the diamond body, a second metal contact, and an optical source or other illuminating or irradiating device such that when the depletion region formed by the Schottky contact to the intrinsic diamond layer is exposed to its radiation charge carriers are generated. Cain in the total number of charge carriers then occurs as a result of these charge carriers accelerating under the field within the intrinsic diamond layer and generating further carriers by assisted avalanche breakdown.
摘要翻译：一种高电压金刚石开关器件，能够以较低阻抗和相对低的光开关通量在导通状态下维持高电流，并且能够在存在正在切换的高电压的情况下被关断。该装置包括具有肖特基势垒接触件的金刚石体，通过施加的被切换的电压以相反的偏置保持在金刚石本体中的基本上本征的金刚石层或部分，第二金属接触和光源或其它照明或照射装置，使得当通过与本征金刚石层的肖特基接触形成的耗尽区域暴露于其辐射电荷载体时。因此，由于这些电荷载流子在本征金刚石层内的场下加速并且通过辅助的雪崩击穿而产生另外的载流子，所以导致电荷载流子总数的隐藏。

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