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61. 发明专利

JPS6477134A METHOD OF ASSEMBLING INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6477134A
公开(公告)日：1989-03-23
申请号：JP23233387
申请日：1987-09-18
申请人： FUJITSU LTD
发明人： MIZUKOSHI MASATAKA
IPC分类号： H01L21/52 , H01L21/60
摘要： PURPOSE:To enable the connection wirings be intersected as well as a large and small wirings to be formed for enhancing the design freedom in the IC chip assembling process by properly using both conductive and insulating pastes. CONSTITUTION:A gap between a package 21 and a semiconductor chip 11 is gently filled up with a groove filler 16 so that the electrodes 12 of said chip 11 and the other electrodes of package may be connected in almost flat state by wirings formed in arbitrary size using a conductive paste 13 while the intersecting parts of said wirings may be insulated using an insulating paste 14. Said pastes 13, 14 are discharged from a fine nozzle to make thread type wirings by decelerating the moving speed of nozzle for making large wirings while accelerating the same for making small wirings. Through these procedures, the design freedom in IC chip assembling process can be enhanced.

62. 发明专利

JPS6345779A WEDGE TOOL FOR ULTRASONIC WIRE BONDING 失效
公开(公告)号：JPS6345779A
公开(公告)日：1988-02-26
申请号：JP18909686
申请日：1986-08-12
申请人： FUJITSU LTD
发明人： MIZUKOSHI MASATAKA
IPC分类号： H01R43/02

63. 发明专利

JPS6344733A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6344733A
公开(公告)日：1988-02-25
申请号：JP18909786
申请日：1986-08-12
申请人： FUJITSU LTD
发明人： MIZUKOSHI MASATAKA
IPC分类号： H01L21/60
摘要： PURPOSE:To raise the packaging density by a method wherein a vertical electrode installed at a package is connected with an electrode installed at a semiconductor chip so that the plane size of a semiconductor device can be reduced. CONSTITUTION:A semiconductor chip 2 is fixed at a concave part 12 of a ceramic package 11. A vertical electrode 13 is formed on a vertical surrounding wall 14 at the concave part 12. In addition, a wire 17 is wired between a part where an electrode 9 on the chip 2 is bonded and another part where the electrode 13 is bonded. Because, according to a semiconductor device 10, the electrode 13 is formed vertically on the surrounding wall 14 at the concave part 12, the plane size of the package 11 can be reduced. Therefore, it is possible to raise the packaging density as compared with the constitution which has been adopted so far.

64. 发明专利

JPS59195856A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS59195856A
公开(公告)日：1984-11-07
申请号：JP7055883
申请日：1983-04-20
申请人： Fujitsu Ltd
发明人： MIZUKOSHI MASATAKA , ENDOU TEIICHI
IPC分类号： H01L21/60 , H01L23/49 , H01L23/498
CPC分类号： H01L24/85 , H01L23/498 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/06153 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/48471 , H01L2224/48599 , H01L2224/48699 , H01L2224/49052 , H01L2224/49109 , H01L2224/49171 , H01L2224/49431 , H01L2224/4945 , H01L2224/78313 , H01L2224/85181 , H01L2224/85186 , H01L2224/85191 , H01L2224/85986 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01074 , H01L2924/01079 , H01L2924/15153 , H01L2924/15165 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/00 , H01L2924/2075 , H01L2224/05599 , H01L2224/85399
摘要： PURPOSE:To reduce contact accidents, and to improve reliability by bonding wires so that the positions of the rise sections and fall sections of adjacent bonding wires are reversed mutually. CONSTITUTION:The directions of bonding of bonding wires connecting connecting pads 1 on a semiconductor chip 10 and connecting electrodes 2 on a semiconductor vessel 20 are all brought to the opposite directions among adjacent connecting pads and among adjacent connecting electrodes as shown in the arrows. According to such wire bonding, since the bonding wire rises high in the rise section of the connecting pad 1 or connecting electrode 2 bonded first and the wire is pulled in the direction of the arrow and is bonded and falls, the wires can be separated mutually at farther intervals in space, and the wires are made difficult to be brought into contact more than a bonding by a pull in the same direction (such as only in the forward direction).
摘要翻译：目的：减少接触事故，并通过接合线提高可靠性，使相邻接合线的上升部分和下降部分的位置相互反向。构成：如图箭头所示，将半导体芯片10上的连接焊盘1和半导体容器20上的连接电极2的接合线的接合方向全部沿着相邻的连接焊盘和相邻的连接电极之间的相反方向。根据这种引线接合，由于接合线在连接焊盘1的上升部分或第一接合电极2的上升部分上升，并且电线沿着箭头方向被拉动并被接合和下降，所以电线可以相互分离在空间中的间隔更远的地方，通过在相同方向（例如仅在向前方向）上的拉动而使得线难以接合。

65. 发明专利

JP2012248598A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2012248598A
公开(公告)日：2012-12-13
申请号：JP2011117722
申请日：2011-05-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA , ISHIZUKI YOSHIKATSU
IPC分类号： H01L21/56 , C09J5/00 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/96 , H01L2224/16 , H01L2924/10253 , H01L2924/15788 , H01L2924/181 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method in which a high density semiconductor device can be manufactured at high yield by integrating a plurality of semiconductor chips or a semiconductor chip with other electronic components with resin.SOLUTION: A semiconductor device manufacturing method comprises: arranging a metal layer 13 on a support substrate 11 via an adhesive layer 12; forming a pressure-sensitive adhesion layer 14 by adhering a solution that reacts with a metal of the metal layer 13 to generate a compound having adhesiveness on the metal layer 13; subsequently, loading an electronic component 15 on the pressure-sensitive adhesion layer 14 and covering the electronic component 15 with a resin layer 16; subsequently, detaching the support substrate 11 from the resin layer 16 after reducing an adhesive force of the adhesive layer 12 with laser irradiation and the like; and subsequently, forming wiring and the like on a surface of a pseudo-wafer obtained by removing the adhesive layer 12, the metal layer 13 and the like.
摘要翻译：解决的问题：提供一种半导体器件制造方法，其中通过将多个半导体芯片或半导体芯片与其他电子部件与树脂集成，可以高产率制造高密度半导体器件。解决方案：半导体器件制造方法包括：通过粘合剂层12将金属层13布置在支撑基板11上; 通过粘附与金属层13的金属反应的溶液以形成在金属层13上具有粘合性的化合物来形成压敏粘合层14; 随后将电子部件15装载在压敏粘合层14上并用树脂层16覆盖电子部件15; 随后，通过激光照射等降低粘合层12的粘合力后，从树脂层16分离支撑基板11; 并且随后在通过去除粘合剂层12，金属层13等获得的伪晶片的表面上形成布线等。版权所有（C）2013，JPO＆INPIT

66. 发明专利

JP2012204523A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012204523A
公开(公告)日：2012-10-22
申请号：JP2011066475
申请日：2011-03-24
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAKAI TAIJI , IMAIZUMI NOBUHIRO , MIZUKOSHI MASATAKA
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L24/75 , H01L2224/11013 , H01L2224/1184 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16245 , H01L2224/75101 , H01L2224/81011 , H01L2224/81065 , H01L2224/81075 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/8183 , H01L2224/83192 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13064 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of achieving highly-reliable bonding while suppressing increase in cost.SOLUTION: Mechanical processing of a surface of a first electrode provided to a semiconductor element is performed to provide a microcrystal first layer having a smaller particle diameter than that before the mechanical processing, and mechanical processing of a surface of a second electrode provided to a mounting member for mounting the semiconductor element is performed to provide a microcrystal second layer having a smaller particle diameter than that before the mechanical processing (step S1). An oxide film existing on a surface of the first layer and an oxide film existing on a surface of the second layer are resolved at a temperature less than a temperature at which a metal configuring the first electrode is solid-phase diffused and less than a temperature at which a metal configuring the second electrode is solid-phase diffused (step S2). The first layer and the second layer are bonded with each other by solid-phase diffusion (step S4).
摘要翻译：要解决的问题：提供一种能够在抑制成本增加的同时实现高可靠性接合的半导体器件的制造方法。解决方案：进行提供给半导体元件的第一电极的表面的机械加工，以提供具有比机械加工之前更小的粒径的微晶第一层，并且提供第二电极的表面的机械加工执行用于安装半导体元件的安装构件，以提供具有比机械处理之前更小的粒径的微晶第二层（步骤S1）。存在于第一层的表面上的氧化物膜和存在于第二层的表面上的氧化膜在比构成第一电极的金属固相扩散的温度低的温度下分辨，并且小于温度配置第二电极的金属是固相扩散的（步骤S2）。第一层和第二层通过固相扩散而彼此接合（步骤S4）。版权所有（C）2013，JPO＆INPIT

67. 发明专利

JP2012054358A Method of manufacturing electronic device 有权
标题翻译：制造电子器件的方法
公开(公告)号：JP2012054358A
公开(公告)日：2012-03-15
申请号：JP2010195004
申请日：2010-08-31
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA , ABE HIDEYUKI
IPC分类号： H01L21/52
CPC分类号： H01L24/29 , H01L2224/32225 , H01L2224/73265 , H01L2224/8384 , H01L2224/92247 , H01L2924/1305 , H01L2924/13055 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To form strong joining between substrates.SOLUTION: A method of manufacturing an electronic apparatus includes: a step of adhering a first substrate and a second substrate via a metallic paste containing metal particles and organic solvent; a step of forming an aggregate of the metal particles by removing the organic solvent from the metallic paste; a step of reducing surfaces of the metal particles constituting the aggregate using reductive gas; and a step of joining the first substrate and the second substrate using the aggregate by pressing the first substrate and the second substrate after a step of reducing the surfaces of the metal particles constituting the aggregate.
摘要翻译：要解决的问题：形成基板之间的强连接。解决方案：一种制造电子设备的方法包括：通过含有金属颗粒和有机溶剂的金属糊粘附第一衬底和第二衬底的步骤; 通过从金属糊中除去有机溶剂来形成金属颗粒的聚集体的步骤; 使用还原气体还原构成集合体的金属粒子的表面的工序; 以及在减少构成聚集体的金属颗粒的表面的步骤之后，通过按压第一基板和第二基板，使用聚集体来接合第一基板和第二基板的步骤。版权所有（C）2012，JPO＆INPIT

68. 发明专利

JP2011242061A Loop type heat pipe, and electronic equipment 有权
标题翻译：环型热管和电子设备
公开(公告)号：JP2011242061A
公开(公告)日：2011-12-01
申请号：JP2010114604
申请日：2010-05-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SHIOGA KENJI , OGATA SHIN , UCHIDA HIROMOTO , AOKI SHIGENORI , MIZUKOSHI MASATAKA
IPC分类号： F28D15/02 , H01L23/427
CPC分类号： F28D15/0266 , F28D15/046
摘要： PROBLEM TO BE SOLVED: To improve the heat transport efficiency of a loop type heat pipe by promoting evaporation of a working fluid on an inner wall of a casing in an evaporation part of the loop type heat pipe.SOLUTION: The evaporation part of the loop type heat pipe includes the casing 140 and a porous wick 132 disposed inside the casing 140. The wick 132 includes pores 132p. A group of projections 141 (142 and 143) is disposed on the inner wall 140a of the casing 140, and at least a part (high projections) 142 of the projection groups 141 is in contact with the wick 132. The projection group 141 guides the working fluid permeating in the wick 132 to the inner wall 140a of the casing by, for example, capillary force, to form a liquid film of the working fluid along the inner wall 140a.
摘要翻译：要解决的问题：通过促进循环式热管的蒸发部件中的壳体内壁上的工作流体的蒸发来提高环路式热管的传热效率。解决方案：环型热管的蒸发部分包括壳体140和设置在壳体140内部的多孔芯132.芯132包括孔132p。一组突起141（142和143）设置在壳体140的内壁140a上，并且突起组141的至少一部分（高突起）142与芯132接触。突起组141引导工作流体通过例如毛细管力渗透到芯132的内壁140a，以沿着内壁140a形成工作流体的液膜。版权所有（C）2012，JPO＆INPIT

69. 发明专利

JP2011179958A Test method and tester of semiconductor circuit 有权
标题翻译：半导体电路的测试方法和测试
公开(公告)号：JP2011179958A
公开(公告)日：2011-09-15
申请号：JP2010044278
申请日：2010-03-01
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA
IPC分类号： G01R31/26 , G01R1/073
摘要： PROBLEM TO BE SOLVED: To provide a test method and tester of a semiconductor circuit, which implements a test in a short period of time at a low cost, and also implements the test in the state where a plurality of the LSI chips are combined without damaging the tester and the LSI chips.
SOLUTION: The problem is overcome by the test method of the semiconductor circuit having: a conductive adhesive applying process for applying a conductive adhesive manufactured by kneading a conductive filler in an organic material solid at a normal temperature, melted at a first temperature and volatile at a second temperature to a surface of an electrode terminal in the semiconductor chip in a state that it is heated at the first temperature or above; a semiconductor chip connecting process for fixing and electrically connecting the electrode terminal of the semiconductor chip to a corresponding electrode terminal of a probe card through the conductive adhesive when the temperature of the conductive adhesive becomes the first temperature or below; a testing process for implementing the test of the semiconductor circuit in the semiconductor chip with respect to the semiconductor chip electrically connected to the probe card; and a semiconductor chip removing process for heating the semiconductor chip electrically connected to the probe card at the second temperature or above, and removing the semiconductor chip from the probe card by volatilizing the organic material.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种以低成本在短时间内进行测试的半导体电路的测试方法和测试器，并且还在多个LSI芯片的状态下进行测试组合而不损坏测试仪和LSI芯片。解决方案：通过具有以下的半导体电路的测试方法来克服该问题：具有导电粘合剂施加工艺，该导电粘合剂施加工艺用于施加通过在常温下将有机材料固体捏合导电填料制成的导电粘合剂，在第一温度并且在第二温度下以在第一温度或更高温度下被加热的状态在半导体芯片中的电极端子的表面上挥发; 半导体芯片连接工艺，当导电粘合剂的温度达到第一温度或更低时，通过导电粘合剂将半导体芯片的电极端子固定和电连接到探针卡的相应电极端子; 用于实现半导体芯片中的半导体电路相对于与探针卡电连接的半导体芯片的测试的测试过程; 以及半导体芯片去除工艺，用于加热在第二温度或更高温度下电连接到探针卡的半导体芯片，并且通过挥发有机材料从探针卡移除半导体芯片。版权所有（C）2011，JPO＆INPIT

70. 发明专利

JP2011029352A Circuit board, electronic apparatus and method for manufacturing the circuit board and the electronic apparatus 有权
标题翻译：电路板，电子设备及制造电路板及电子设备的方法
公开(公告)号：JP2011029352A
公开(公告)日：2011-02-10
申请号：JP2009172604
申请日：2009-07-24
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA
IPC分类号： H01L21/60
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a structure pressing an electronic component on a circuit board to detachably mount it with low contact resistance wherein the electronic component includes a first electrode having carbon nanotubes implanted thereto. SOLUTION: A circuit board 1 has a second electrode 11 formed on the circuit board 1, wherein a tip of each of carbon nanotubes 23 contacts with the second electrode 11, so that the second electrode 11 is electrically connected with a first electrode 21. The second electrode 11 has: an electrode pad 12 disposed on an upper surface of the circuit board 1; and conductive cone-shaped projections 13 formed on an upper surface of the electrode pad 12 in a frog-like shape. Since each carbon nanotube 23 contacts linearly with each projection at a side surface of each carbon nanotube 23, low contact resistance is achieved even by pressing at a low pressure within an elastic limit of the carbon nanotubes 23. In addition, since no plastic deformation occurs in the carbon nanotubes 23, reconnection can be performed. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种将电子部件按压在电路板上的结构，以便以低接触电阻可拆卸地安装该结构，其中电子部件包括其中植入有碳纳米管的第一电极。解决方案：电路板1具有形成在电路板1上的第二电极11，其中每个碳纳米管23的尖端与第二电极11接触，使得第二电极11与第一电极第二电极11具有：设置在电路板1的上表面上的电极焊盘12; 以及以蛙状形成在电极焊盘12的上表面上的导电锥形突起13。由于每个碳纳米管23与每个碳纳米管23的侧表面处的每个突起线性地接触，所以即使在碳纳米管23的弹性极限内的低压下压制也可以实现低接触电阻。此外，由于没有发生塑性变形在碳纳米管23中，可以进行重新连接。版权所有（C）2011，JPO＆INPIT

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