专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06538464B2 Slew rate control 有权
公开(公告)号：US06538464B2
公开(公告)日：2003-03-25
申请号：US09925345
申请日：2001-08-09
申请人： Harry Muljono , Alper Ilkbahar
发明人： Harry Muljono , Alper Ilkbahar
IPC分类号： H03K1716
CPC分类号： H03K19/0005 , H03K19/018585
摘要： Controlling the slew rate of a driver circuit. According to one embodiment of the present invention an output buffer includes a driver circuit having an impedance and a pre-driver circuit to control a slew rate of the driver circuit based on the impedance of the driver circuit.

62. 发明授权

US06531745B1 Electro static discharge protection n-well ballast resistor device 失效
公开(公告)号：US06531745B1
公开(公告)日：2003-03-11
申请号：US09475728
申请日：1999-12-30
申请人： Bruce Woolery , Alper Ilkbahar
发明人： Bruce Woolery , Alper Ilkbahar
IPC分类号： H01L2362
CPC分类号： H01L27/0629 , H01L27/0288
摘要： An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.

63. 发明授权

US06317801B1 System for post-driving and pre-driving bus agents on a terminated data bus 失效
标题翻译：终端数据总线上的后驱动和预驱动总线代理系统
公开(公告)号：US06317801B1
公开(公告)日：2001-11-13
申请号：US09123097
申请日：1998-07-27
申请人： Alper Ilkbahar , Kent R. Townley
发明人： Alper Ilkbahar , Kent R. Townley
IPC分类号： G06F300
CPC分类号： G06F13/4086
摘要： A method and apparatus for post-driving and pre-driving a terminated bus that shortens dead cycles on a bus during bus master change-overs. In one embodiment, a first bus agent giving up control of the bus drives the bus to termination voltage levels during a first portion of the dead cycle. A second bus agent gaining control of the bus also drives the bus to termination voltage levels during a last portion of the dead cycle. For the time period between the first portion and the second portion, termination components such as resistors or transistors maintain the bus at termination voltage levels. By driving the bus to termination voltage levels with bus agents, bus transients are settled more quickly than with termination components alone, which improves performance of the bus over configurations pulled to termination voltage levels with termination components alone.
摘要翻译：一种用于后期驱动和预驱动终端总线的方法和装置，其在总线主机切换期间缩短总线上的死循环。在一个实施例中，放弃对总线的控制的第一总线代理在总线周期的第一部分期间将总线驱动到终端电压电平。获得对总线控制的第二总线代理也驱动总线在死循环的最后部分期间的终止电压电平。对于第一部分和第二部分之间的时间段，诸如电阻器或晶体管的端接部件将总线保持在终止电压电平。通过使用总线代理将总线驱动到终端电压电平，总线瞬变比单独使用终端组件更快地进行安装，这样可以提高总线的性能，而这种配置仅通过端接组件被拉至终端电压电平。

64. 发明授权

US06026456A System utilizing distributed on-chip termination 失效
标题翻译：利用分布式片上终端的系统
公开(公告)号：US06026456A
公开(公告)日：2000-02-15
申请号：US573568
申请日：1995-12-15
申请人： Alper Ilkbahar
发明人： Alper Ilkbahar
IPC分类号： G06F13/40 , H03K17/16 , G06F13/00 , H03K19/094
CPC分类号： G06F13/4086
摘要： A system utilizing distributed on-chip termination. The system comprises a bus having a signal line and a first bus agent which is coupled to the bus. The first bus agent has a first termination circuit which is coupled to selectably terminate the signal line to a termination voltage. The system may further comprise an additional bus agent. The additional bus agent has a second termination circuit coupled to selectably terminate the signal line to the termination voltage. The bus in the system has a bus impedance, and the impedance of the termination circuit(s) is typically greater than twice the bus impedance.
摘要翻译：一种利用分布式片上终端的系统。该系统包括具有信号线的总线和耦合到总线的第一总线代理。第一总线代理具有第一终端电路，其被耦合以可选择地将信号线终止到终止电压。该系统还可以包括附加的总线代理。附加总线代理具有耦合到可选择地将信号线终止到终止电压的第二终端电路。系统中的总线具有总线阻抗，并且终端电路的阻抗通常大于总线阻抗的两倍。

65. 发明授权

US5517136A Opportunistic time-borrowing domino logic 失效
标题翻译：机会时间借贷多米诺骨牌
公开(公告)号：US5517136A
公开(公告)日：1996-05-14
申请号：US398123
申请日：1995-03-03
申请人： David Harris , Sunny C. Huang , James Nadir , Ching-Hua Chu , Jason C. Stinson , Alper Ilkbahar
发明人： David Harris , Sunny C. Huang , James Nadir , Ching-Hua Chu , Jason C. Stinson , Alper Ilkbahar
IPC分类号： H03K19/017 , H03K19/096
CPC分类号： H03K19/01728 , H03K19/0963
摘要： An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.
摘要翻译：机会时间借用多米诺骨牌包括具有串联耦合并由第一，第二，第三和第四时钟信号控制的多个逻辑门的多米诺河流管线。半周期中的第一个多米诺骨门由第一或第二时钟信号计时，其中半周期中最后的多米诺门由第三或第四个时钟周期计时。第二时钟信号是第一时钟信号的倒数，并且第三和第四时钟信号具有本地延迟的时钟相位，其中第三和第四时钟信号的下降沿相对于相应的第一和第二时钟信号的下降沿被延迟时钟信号。在第一个半周期中，第一种类型的多米诺式门由第一时钟信号控制，同一类型的后续多米诺式门由第三时钟信号控制。奇数半周期以由第二时钟信号控制的第二类型的多米诺门开始，其后是由第四时钟信号控制的第一类型的多米诺门。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式