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61. 发明申请

US20120132913A1 III-V Compound Semiconductor Material Passivation With Crystalline Interlayer 有权
标题翻译： III-V复合半导体材料钝化与结晶中间层
公开(公告)号：US20120132913A1
公开(公告)日：2012-05-31
申请号：US12955203
申请日：2010-11-29
申请人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
发明人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译：本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

62. 发明申请

US20110121370A1 EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于半导体结构的嵌入式压电器
公开(公告)号：US20110121370A1
公开(公告)日：2011-05-26
申请号：US12625827
申请日：2009-11-25
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.
摘要翻译：一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极叠层相邻的衬底的侧壁部分，应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

63. 发明授权

US08513131B2 Fin field effect transistor with variable channel thickness for threshold voltage tuning 有权
标题翻译：具有可变通道厚度的Fin场效应晶体管用于阈值电压调谐
公开(公告)号：US08513131B2
公开(公告)日：2013-08-20
申请号：US13050101
申请日：2011-03-17
申请人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
IPC分类号： H01L21/311
CPC分类号： H01L27/0886 , H01L21/3086 , H01L21/845 , H01L27/1211
摘要： A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
摘要翻译：一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

64. 发明申请

US20120235247A1 FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING 有权
标题翻译：具有用于阈值电压调谐的可变通道厚度的FIN场效应晶体管
公开(公告)号：US20120235247A1
公开(公告)日：2012-09-20
申请号：US13050101
申请日：2011-03-17
申请人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
IPC分类号： H01L27/088 , H01L21/32
CPC分类号： H01L27/0886 , H01L21/3086 , H01L21/845 , H01L27/1211
摘要： A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
摘要翻译：一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

65. 发明授权

US08895372B2 Graphene based three-dimensional integrated circuit device 有权
标题翻译：石墨烯三维集成电路器件
公开(公告)号：US08895372B2
公开(公告)日：2014-11-25
申请号：US13557501
申请日：2012-07-25
申请人： Dechao Guo , Shu-Jen Hen , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Hen , Chung-Hsun Lin , Ning Su
IPC分类号： H01L21/84 , H01L27/06 , H01L29/16
CPC分类号： H01L27/0688 , H01L29/1606 , Y10S977/755
摘要： A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.
摘要翻译：三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

66. 发明授权

US08450779B2 Graphene based three-dimensional integrated circuit device 有权
标题翻译：石墨烯三维集成电路器件
公开(公告)号：US08450779B2
公开(公告)日：2013-05-28
申请号：US12719058
申请日：2010-03-08
申请人： Dechao Guo , Shu-Jen Hen , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Hen , Chung-Hsun Lin , Ning Su
IPC分类号： H01L23/52
CPC分类号： H01L27/0688 , H01L29/1606 , Y10S977/755
摘要： A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.
摘要翻译：三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

67. 发明授权

US08729637B2 Work function adjustment by carbon implant in semiconductor devices including gate structure 有权
标题翻译：通过碳植入在包括栅极结构的半导体器件中进行功能调整
公开(公告)号：US08729637B2
公开(公告)日：2014-05-20
申请号：US13253268
申请日：2011-10-05
申请人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
发明人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
IPC分类号： H01L21/70 , H01L21/20 , H01L21/00
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/823857 , H01L29/1054 , H01L29/517
摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
摘要翻译：一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。还公开了形成上述装置的方法。

68. 发明申请

US20130105896A1 Threshold Voltage Adjustment For Thin Body Mosfets 审中-公开
标题翻译：薄体硅片的阈值电压调整
公开(公告)号：US20130105896A1
公开(公告)日：2013-05-02
申请号：US13625350
申请日：2012-09-24
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。

69. 发明授权

US09312358B2 Partially-blocked well implant to improve diode ideality with SiGe anode 有权
公开(公告)号：US09312358B2
公开(公告)日：2016-04-12
申请号：US13617140
申请日：2012-09-14
申请人： Dechao Guo , Wilfried E. Haensch , Gan Wang , Yanfeng Wang , Xin Wang
发明人： Dechao Guo , Wilfried E. Haensch , Gan Wang , Yanfeng Wang , Xin Wang
IPC分类号： H01L29/66 , H01L29/739 , H01L29/165 , H01L29/16
CPC分类号： H01L29/66356 , H01L29/1608 , H01L29/165 , H01L29/7391
摘要： A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

70. 发明授权

US09040399B2 Threshold voltage adjustment for thin body MOSFETs 有权
标题翻译：薄体MOSFET的阈值电压调整
公开(公告)号：US09040399B2
公开(公告)日：2015-05-26
申请号：US13282619
申请日：2011-10-27
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
IPC分类号： H01L21/425 , H01L29/66
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。还公开了制造FinFET晶体管的方法。还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

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