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61. 发明授权

US07877710B1 Method and apparatus for deriving signal activities for power analysis and optimization 有权
标题翻译：用于导出功率分析和优化的信号活动的方法和装置
公开(公告)号：US07877710B1
公开(公告)日：2011-01-25
申请号：US11414855
申请日：2006-05-01
申请人： David Neto , Vaughn Betz , Meghal Varia , Gregg William Baeckler
发明人： David Neto , Vaughn Betz , Meghal Varia , Gregg William Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures.
摘要翻译：用于管理无向量估计的方法包括识别语义结构。信号活动被分配给语义结构的输出。对非语义结构进行无矢量估计。

62. 发明授权

US07725853B1 Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权
标题翻译：优化长途径和短路时间，并对制造和运行状况变化进行考虑
公开(公告)号：US07725853B1
公开(公告)日：2010-05-25
申请号：US11857316
申请日：2007-09-18
申请人： Ryan Fung , Vaughn Betz
发明人： Ryan Fung , Vaughn Betz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.
摘要翻译：优化逻辑设计，以满足多个过程/操作条件角的长途径和短路时序约束。基于路径的编译阶段确定逻辑设计路径的实现，部分地通过监视从时序角度重要的一组路径并且评估一个或多个定时角上的一组被监控路径的定时性能。基于时序分析的编译阶段确定将一组定时值从一个定时角转换到另一个时间角的转换。编译阶段将时序延迟值从一个定时角转换到另一个定时角，以便于分析不同角落的时序性能。通过分析产生的时间松弛值被转换，以将它们从一个时间点转到另一个时间点。来自多个角落的转换后的时间松弛值是合并的。合并的定时松弛值由编译阶段（可能只能理解单个角）使用，以优化多个角的逻辑设计。

63. 发明申请

US20100070979A1 Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software 审中-公开
标题翻译：并联集成电路计算机辅助设计软件的装置与方法
公开(公告)号：US20100070979A1
公开(公告)日：2010-03-18
申请号：US12545224
申请日：2009-08-21
申请人： Adrian Ludwin , Vaughn Betz , Ketan Padalia
发明人： Adrian Ludwin , Vaughn Betz , Ketan Padalia
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483 , G06F2209/484
摘要： A system for parallelizing software in computer-aided design (CAD) software for logic design includes a computer. The computer is configured to identify dependencies among a set of tasks. The computer is also configured to perform the set of tasks in parallel such that a solution of a problem is identical to a solution produced by performing the set of tasks serially.
摘要翻译：用于并行化用于逻辑设计的计算机辅助设计（CAD）软件中的软件的系统包括计算机。计算机被配置为识别一组任务之间的依赖关系。计算机还被配置为并行地执行一组任务，使得问题的解决方案与通过一致地执行该任务所产生的解决方案相同。

64. 发明授权

US07467314B2 Systems and methods for reducing static and total power consumption in a programmable logic device 失效
标题翻译：用于减少可编程逻辑器件中的静态和总功耗的系统和方法
公开(公告)号：US07467314B2
公开(公告)日：2008-12-16
申请号：US11642287
申请日：2006-12-19
申请人： David Mendel , Vaughn Betz
发明人： David Mendel , Vaughn Betz
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/32
摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
摘要翻译：提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

65. 发明授权

US07441208B1 Methods for designing integrated circuits 有权
标题翻译：集成电路设计方法
公开(公告)号：US07441208B1
公开(公告)日：2008-10-21
申请号：US11225919
申请日：2005-09-13
申请人： Ketan Padalia , Vaughn Betz , Vadim Gouterman
发明人： Ketan Padalia , Vaughn Betz , Vadim Gouterman
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process. This signoff preferably takes place after at least some global routing has been done for the IC implementation, but before all final detailed routing is done for that implementation.
摘要翻译：设计集成电路（“IC”）以实现广义电路设计的过程包括过程的前端部分与过程的后端部分之间的签名。这种签名优选在对IC实现进行至少一些全局路由之后，但在为该实现完成所有最终详细路由之前进行。

66. 发明授权

US07412680B1 Method and apparatus for performing integrated global routing and buffer insertion 有权
标题翻译：用于执行集成全局路由和缓冲区插入的方法和装置
公开(公告)号：US07412680B1
公开(公告)日：2008-08-12
申请号：US11227680
申请日：2005-09-15
申请人： Vadim Gouterman , Vaughn Betz , Mark Bourgeault
发明人： Vadim Gouterman , Vaughn Betz , Mark Bourgeault
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/505
摘要： A method for designing a system on an integrated circuit includes synthesizing the system. The system is placed on the integrated circuit. Buffer insertion is performed while selecting new branch points during routing of the system.
摘要翻译：集成电路中的系统的设计方法包括合成该系统。该系统放置在集成电路上。在系统路由期间选择新的分支点时执行缓冲区插入。

67. 发明申请

US20070192766A1 Apparatus and methods for parallelizing integrated circuit computer-aided design software 审中-公开
标题翻译：用于并行集成电路计算机辅助设计软件的装置和方法
公开(公告)号：US20070192766A1
公开(公告)日：2007-08-16
申请号：US11392215
申请日：2006-03-29
申请人： Ketan Padalia , Adrian Ludwin , Vaughn Betz , Ryan Fung
发明人： Ketan Padalia , Adrian Ludwin , Vaughn Betz , Ryan Fung
IPC分类号： G06F9/46
CPC分类号： G06F8/45 , G06F17/5054
摘要： A system for providing parallelization in computer aided design (CAD) software includes a computer. The computer is configured to identify a set of tasks having local independence, and assign each task in the set of tasks to be performed in parallel. The computer is further configured to perform each task in the set of tasks.
摘要翻译：用于在计算机辅助设计（CAD）软件中提供并行化的系统包括计算机。计算机被配置为识别具有本地独立性的一组任务，并且将要并行执行的任务集中的每个任务分配。计算机还被配置为在该组任务中执行每个任务。

68. 发明授权

US07254789B1 Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权
公开(公告)号：US07254789B1
公开(公告)日：2007-08-07
申请号：US11002977
申请日：2004-12-01
申请人： Ryan Fung , Vaughn Betz
发明人： Ryan Fung , Vaughn Betz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.

69. 发明授权

US07181703B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07181703B1
公开(公告)日：2007-02-20
申请号：US10625505
申请日：2003-07-22
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

70. 发明授权

US06828824B2 Heterogeneous interconnection architecture for programmable logic devices 失效
公开(公告)号：US06828824B2
公开(公告)日：2004-12-07
申请号：US10449753
申请日：2003-05-30
申请人： Vaughn Betz , Jonathan Rose
发明人： Vaughn Betz , Jonathan Rose
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

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