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61. 发明授权

US08569104B2 Transition metal oxide bilayers 有权
公开(公告)号：US08569104B2
公开(公告)日：2013-10-29
申请号：US13367927
申请日：2012-02-07
申请人： Hieu Pham , Vidyut Gopal , Imran Hashim , Tim Minvielle , Yun Wang , Takeshi Yamaguchi , Hong Sheng Yang
发明人： Hieu Pham , Vidyut Gopal , Imran Hashim , Tim Minvielle , Yun Wang , Takeshi Yamaguchi , Hong Sheng Yang
IPC分类号： H01L29/02
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

62. 发明授权

US08551851B2 Titanium-based high-K dielectric films 有权
标题翻译：钛基高K电介质薄膜
公开(公告)号：US08551851B2
公开(公告)日：2013-10-08
申请号：US13100538
申请日：2011-05-04
申请人： Hanhong Chen , Pragati Kumar , Sunil Shanker , Edward Haywood , Sandra Malhotra , Imran Hashim , Nobi Fuchigami , Prashant Phatak , Monica Mathur
发明人： Hanhong Chen , Pragati Kumar , Sunil Shanker , Edward Haywood , Sandra Malhotra , Imran Hashim , Nobi Fuchigami , Prashant Phatak , Monica Mathur
IPC分类号： H01L21/20
CPC分类号： H01G4/1218 , C23C16/405 , C23C16/45531 , C23C16/56 , H01G4/33 , H01L21/02186 , H01L21/022 , H01L21/0228 , H01L21/02312 , H01L21/02337 , H01L21/3141 , H01L21/3142 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.
摘要翻译：本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于使用含酰胺的前体的TiO 2电介质。在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

63. 发明申请

US20130134376A1 ATOMIC LAYER DEPOSITION OF ZIRCONIUM OXIDE FOR FORMING RESISTIVE-SWITCHING MATERIALS 有权
标题翻译：用于形成电阻开关材料的氧化锆原子层沉积
公开(公告)号：US20130134376A1
公开(公告)日：2013-05-30
申请号：US13306096
申请日：2011-11-29
申请人： Jinhong Tong , Vidyut Gopal , Imran Hashim , Randall Higuchi , Albert Lee
发明人： Jinhong Tong , Vidyut Gopal , Imran Hashim , Randall Higuchi , Albert Lee
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/08 , H01L27/2463 , H01L45/146 , H01L45/1616
摘要： Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium oxide for use in a variety of electronic devices. Forming the dielectric layer includes depositing zirconium oxide using atomic layer deposition. A method of atomic layer deposition to produce a metal-rich metal oxide comprises the steps of providing a silicon substrate in a reaction chamber, pulsing a zirconium precursor for a predetermined time to deposit a first layer, and oxidizing the first layer with water vapor to produce the metal-rich metal oxide. The metal-rich metal oxide has superior properties for non-volatile resistive-switching memories.
摘要翻译：原子层沉积（ALD）可用于形成用于各种电子器件的氧化锆电介质层。形成介电层包括使用原子层沉积沉积氧化锆。原子层沉积法生产富金属的金属氧化物的方法包括以下步骤：在反应室中提供硅衬底，将锆前体脉冲预定的时间以沉积第一层，并用水蒸气氧化第一层产生富金属的金属氧化物。富金属的金属氧化物具有优异的非易失性电阻式开关存储器的性能。

64. 发明申请

US20130065377A1 INTERFACE LAYER IMPROVEMENTS FOR NONVOLATILE MEMORY APPLICATIONS 审中-公开
标题翻译：界面层对非易失性存储器应用的改进
公开(公告)号：US20130065377A1
公开(公告)日：2013-03-14
申请号：US13228744
申请日：2011-09-09
申请人： Vidyut Gopal , Yun Wang , Imran Hashim
发明人： Vidyut Gopal , Yun Wang , Imran Hashim
IPC分类号： H01L47/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1616 , H01L45/1641
摘要： A resistive switching nonvolatile memory device having an interface layer disposed between a doped silicon electrode and a variable resistance layer fabricated in the nonvolatile memory device and methods of fabricating the same. In one embodiment, the interface layer is a high-k layer having a lower electrical EOT than native silicon oxide to act as a diffusion barrier between the variable resistance layer and the silicon electrode. Alternatively, the high-k interface layer may be formed by performing a nitrogen treatment on a fabricated silicon oxide layer. In another embodiment, the interface layer may be fabricated by performing a nitrogen or ozone treatment on the native oxide layer. In another embodiment, the interface layer is a fabricated silicon oxide layer resulting in an improved diffusion barrier between the variable resistance layer and the silicon electrode. In all embodiments, the interface layer also passivates the surface of the silicon electrode.
摘要翻译：一种电阻式开关非易失性存储器件，其具有设置在非易失性存储器件中制造的掺杂硅电极和可变电阻层之间的界面层及其制造方法。在一个实施例中，界面层是具有比天然氧化硅更低的电EOT的高k层，以在可变电阻层和硅电极之间充当扩散势垒。或者，可以通过对制造的氧化硅层进行氮处理来形成高k界面层。在另一个实施方案中，界面层可以通过在自然氧化物层上进行氮气或臭氧处理来制造。在另一个实施例中，界面层是制造的氧化硅层，从而在可变电阻层和硅电极之间形成改善的扩散势垒。在所有实施例中，界面层还钝化硅电极的表面。

65. 发明申请

US20130056702A1 ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS 有权
标题翻译：用于存储器应用的金属氧化物材料的原子层沉积
公开(公告)号：US20130056702A1
公开(公告)日：2013-03-07
申请号：US13612000
申请日：2012-09-12
申请人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiang
发明人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiang
IPC分类号： H01L45/00 , B82Y10/00 , B82Y99/00
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译：本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。设置在金属氧化物层之间的界面有助于氧空位移动。在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对准的晶界，其包含平行于电极界面延伸的许多晶界。因此，氧空缺在切换期间被捕获和释放，而空位明显损失。因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

66. 发明申请

US20130056700A1 DEFECT GRADIENT TO BOOST NONVOLATILE MEMORY PERFORMANCE 有权
标题翻译：缺陷增强非易失性存储器性能
公开(公告)号：US20130056700A1
公开(公告)日：2013-03-07
申请号：US13223950
申请日：2011-09-01
申请人： Yun Wang , Tony Chiang , Imran Hashim
发明人： Yun Wang , Tony Chiang , Imran Hashim
IPC分类号： H01L45/00
CPC分类号： H01L45/122 , H01L27/2463 , H01L45/08 , H01L45/146 , H01L45/1608
摘要： Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter portion and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects as compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects as compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process. The addition of the getter or defect portions in a formed memory device generally improves the reliability of the resistive switching memory device, improves the switching characteristics of the formed memory device and can eliminate or reduce the need for the time consuming additional post fabrication “burn-in” or pre-programming steps.
摘要翻译：本发明的实施例一般涉及一种电阻式开关非易失性存储元件，其形成在电阻式开关存储器件中，其可用于存储阵列中以存储数字数据。存储元件通常构造为金属 - 绝缘体 - 金属叠层。存储元件的电阻开关部分包括吸气部分和/或缺陷部分。通常，吸气剂部分是存储元件的区域，其用于帮助在电阻式开关存储器件的制造过程期间形成与其余部分相比具有更多数量的空位或缺陷的电阻式开关层的区域的电阻式开关层。缺陷部分是与电阻开关层的其余部分相比具有更多数量的空位或缺陷的存储元件的区域，并且在电阻式开关存储器件的制造过程期间形成。吸收剂或缺陷部分在形成的存储器件中的添加通常提高了电阻式开关存储器件的可靠性，改进了所形成的存储器件的开关特性，并且可以消除或减少对耗时的附加后制造烧坏的需要或预编程步骤。

67. 发明申请

US20130028003A1 NONVOLATILE MEMORY DEVICE HAVING A CURRENT LIMITING ELEMENT 有权
标题翻译：具有电流限制元件的非易失性存储器件
公开(公告)号：US20130028003A1
公开(公告)日：2013-01-31
申请号：US13353000
申请日：2012-01-18
申请人： Yun Wang , Imran Hashim , Tony Chiang
发明人： Yun Wang , Imran Hashim , Tony Chiang
IPC分类号： H01L45/00 , H01L21/8239 , G11C11/21
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.
摘要翻译：本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。形成的限流层或电阻层的电性能被配置为通过在形成的电阻中添加固定的串联电阻来在逻辑状态编程步骤（即，设置和复位步骤）期间降低通过可变电阻层的电流在非易失性存储器件中发现的切换存储器元件。

68. 发明授权

US08288297B1 Atomic layer deposition of metal oxide materials for memory applications 有权
标题翻译：用于记忆应用的金属氧化物材料的原子层沉积
公开(公告)号：US08288297B1
公开(公告)日：2012-10-16
申请号：US13224021
申请日：2011-09-01
申请人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiag
发明人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiag
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译：本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。设置在金属氧化物层之间的界面有助于氧空位移动。在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。因此，氧空缺在切换期间被捕获和释放，而空位明显损失。因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

69. 发明申请

US20120171839A1 FABRICATION OF SEMICONDUCTOR STACKS WITH RUTHENIUM-BASED MATERIALS 有权
标题翻译：用基于金属的材料制造半导体堆叠
公开(公告)号：US20120171839A1
公开(公告)日：2012-07-05
申请号：US13395071
申请日：2009-09-18
申请人： Hanhong Chen , Nobumichi Fuchigami , Imran Hashim , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Hanhong Chen , Nobumichi Fuchigami , Imran Hashim , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/02
CPC分类号： C23C16/45531 , C23C16/0272 , C23C16/0281 , C23C16/405 , H01L21/02186 , H01L21/02194 , H01L21/02197 , H01L21/0228 , H01L21/02304 , H01L27/10852 , H01L28/40 , H01L28/65 , H01L28/75
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).
摘要翻译：本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。特别地，要生长电介质层的底部电极可以具有钌基表面。钌表面与电介质层的晶格匹配（例如氧化钛，钛酸锶钛酸钡或钛酸钡锶）有助于促进金红石相二氧化钛的生长，从而导致更高的介电常数和更低的有效氧化物厚度。钌基材料还提供高功函数材料，导致较低的泄漏。为了减轻与使用钌有关的成核延迟，可以采用基于钛的粘附层或胶层。可以进一步采用预处理工艺，以增加有效的电容器板面积，从而进一步提高介电常数和有效的氧化物厚度（“EOT”）。

70. 发明申请

US20120149137A1 Methods of Combinatorial Processing For Screening Multiple Samples on a Semiconductor Substrate 失效
标题翻译：用于在半导体衬底上筛选多个样品的组合处理方法
公开(公告)号：US20120149137A1
公开(公告)日：2012-06-14
申请号：US13399719
申请日：2012-02-17
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： H01L21/66
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

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