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61. 发明授权

US07369616B2 Simultaneous multi-band transmission on a printed circuit board 有权
标题翻译：在印刷电路板上同时进行多频带传输
公开(公告)号：US07369616B2
公开(公告)日：2008-05-06
申请号：US10373364
申请日：2003-02-24
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H04L27/00
CPC分类号： H04L5/06
摘要： The present invention is an apparatus and method for increasing the amount of data on a transmission path on a printed circuit board. Conventional methods allow only one data signal to be transmitted on the transmission path. The present invention uses multiple transmitters to modulate multiple data signals to form multiple modulated signals. The modulated signals are transmitted, possibly simultaneously, on the transmission path to receivers configured to demodulate individual modulated signals and recover the original data signals.
摘要翻译：本发明是用于增加印刷电路板上的传输路径上的数据量的装置和方法。传统方法仅允许在传输路径上传送一个数据信号。本发明使用多个发射机来调制多个数据信号以形成多个调制信号。调制信号可能同时在传输路径上被发送到被配置为解调各个调制信号并恢复原始数据信号的接收机。

62. 发明授权

US07283070B1 Dynamic calibration of I/O power supply level 有权
标题翻译：动态校准I / O电源电平
公开(公告)号：US07283070B1
公开(公告)日：2007-10-16
申请号：US10741680
申请日：2003-12-19
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H03M7/40
CPC分类号： G06F1/26 , G06F11/24
摘要： An input/output interface is used to transmit data between a transmitting circuit and a receiving circuit. Selectively during both system startup and system operation, a known bit pattern transmitted by the transmitting circuit is compared to a received bit pattern. The received bit pattern may be seen at the receiving circuit or a voltage regulator that is used to control the power supply level of the input/output interface. Dependent on the comparison of the known bit pattern and the received bit pattern, a bit error rate across the input/output interface is determined, in response to which the voltage regulator adjusts the power supply level of the input/output interface.
摘要翻译：输入/输出接口用于在发送电路和接收电路之间传输数据。在系统启动和系统操作期间选择性地，由发送电路发送的已知位模式与接收的位模式进行比较。可以在接收电路处看到接收到的位模式，或者用于控制输入/输出接口的电源电平的电压调节器。取决于已知位模式与接收位模式的比较，确定输入/输出接口两端的误码率，响应于此，电压调节器调节输入/输出接口的电源电平。

63. 发明授权

US07251305B2 Method and apparatus to store delay locked loop biasing parameters 有权
标题翻译：存储延迟锁定环偏置参数的方法和装置
公开(公告)号：US07251305B2
公开(公告)日：2007-07-31
申请号：US10147838
申请日：2002-05-17
申请人： Claude R. Gauthier , Brian Amick , Dean Liu , Pradeep Trivedi
发明人： Claude R. Gauthier , Brian Amick , Dean Liu , Pradeep Trivedi
IPC分类号： H03D3/24
CPC分类号： H03L7/0812
摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.
摘要翻译：提供了一种用于延迟锁定环偏置发生器的后制造控制的校准和调整系统。校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。可以存储和随后读取偏置 - 发生器输出中期望的调节量的代表值来调整延迟锁定环。

64. 发明授权

US07190719B2 Impedance controlled transmitter with adaptive compensation for chip-to-chip communication 有权
标题翻译：具有自适应补偿的阻抗控制发射机，用于芯片到芯片的通信
公开(公告)号：US07190719B2
公开(公告)日：2007-03-13
申请号：US10338360
申请日：2003-01-08
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： A method and apparatus for adjusting a frequency characteristic of a signal is provided. A transmitter circuit uses a driver circuit and a filter to generate the signal. The frequency characteristic of the signal is adjusted, or “equalized,” using a replica driver that adjusts the driver circuit and a voltage control circuit that adjusts the filter.
摘要翻译：提供了一种用于调整信号的频率特性的方法和装置。发射机电路使用驱动电路和滤波器来产生信号。使用调整驱动电路的复制驱动器和调整滤波器的电压控制电路对信号的频率特性进行调整或“均衡”。

65. 发明授权

US07106113B2 Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver 有权
公开(公告)号：US07106113B2
公开(公告)日：2006-09-12
申请号：US10147841
申请日：2002-05-17
申请人： Claude R. Gauthier , Brian Amick , Pradeep Trivedi , Dean Liu
发明人： Claude R. Gauthier , Brian Amick , Pradeep Trivedi , Dean Liu
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , G06F1/10 , H03L7/0891 , H03L7/18
摘要： An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

66. 发明授权

US07069459B2 Clock skew reduction technique based on distributed process monitors 有权
标题翻译：基于分布式过程监视器的时钟偏差减少技术
公开(公告)号：US07069459B2
公开(公告)日：2006-06-27
申请号：US10385414
申请日：2003-03-10
申请人： Claude R. Gauthier , Shaishav Desai
发明人： Claude R. Gauthier , Shaishav Desai
IPC分类号： G06F1/12
CPC分类号： G06F1/10
摘要： A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.
摘要翻译：用于调整时钟偏移的方法和装置涉及使用分布在该装置上的多个振荡器，其中多个振荡器中的至少一个具有取决于装置的特性的频率。处理器被布置成根据频率调整偏置发生器。偏置发生器布置成通过可调缓冲器来调节延迟。可调缓冲器被布置为根据取决于偏置发生器的可调谐缓冲器的延迟调整而传播时钟信号。

67. 发明授权

US07043683B2 Data transmission update technique in low power modes 有权
标题翻译：低功耗模式下的数据传输更新技术
公开(公告)号：US07043683B2
公开(公告)日：2006-05-09
申请号：US10360312
申请日：2003-02-07
申请人： Brian W. Amick , Claude R. Gauthier , Aninda Roy
发明人： Brian W. Amick , Claude R. Gauthier , Aninda Roy
IPC分类号： G03M13/00 , G01R31/28
CPC分类号： G06F1/3209 , H04J3/06 , H04L7/0037
摘要： A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.
摘要翻译：提供了一种用于计算机系统的低功率模式和/或低活动模式的数据传输更新技术或其一部分。当处于低功率模式和/或低活动模式时，该技术启动对数据传输的测试，其结果用于调整数据接收的时间，以便促进准确和及时的日期通信。

68. 发明授权

US07017086B2 Round-robin updating for high speed I/O parallel interfaces 有权
标题翻译：高速I / O并行接口循环更新
公开(公告)号：US07017086B2
公开(公告)日：2006-03-21
申请号：US10174045
申请日：2002-06-18
申请人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
发明人： Aninda K. Roy , Claude R. Gauthier , Brian W. Amick
IPC分类号： G01R31/28
CPC分类号： G01R31/31727
摘要： A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.
摘要翻译：用于调整通信系统的技术涉及多个链路，其中每个链路包括适于传输数据信号的数据线和适于发送时钟信号的时钟线。测试电路连接到测试电路测试多个链路中的至少一个的多个链路。测试电路包括调整电路，该调整电路被布置成基于偏移量从多个链路中的一个链路的时钟信号产生可调节时钟信号，其中调整电路相对于一个数据信号调整可调节时钟信号的定时的多个链接。该测试电路适用于执行多个链路的循环测试。

69. 发明授权

US06996491B2 Method and system for monitoring and profiling an integrated circuit die temperature 有权
公开(公告)号：US06996491B2
公开(公告)日：2006-02-07
申请号：US10079476
申请日：2002-02-19
申请人： Spencer M. Gold , Claude R. Gauthier , Steven R. Boyle , Kenneth A. House , Joseph Siegel
发明人： Spencer M. Gold , Claude R. Gauthier , Steven R. Boyle , Kenneth A. House , Joseph Siegel
IPC分类号： G01K1/08
CPC分类号： G06F1/206
摘要： A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

70. 发明授权

US06973398B2 System level reduction of clock skew based on local thermal profiling 有权
标题翻译：基于局部热分析的系统级降低时钟偏移
公开(公告)号：US06973398B2
公开(公告)日：2005-12-06
申请号：US10385346
申请日：2003-03-10
申请人： Claude R. Gauthier , Pradeep R. Trivedi
发明人： Claude R. Gauthier , Pradeep R. Trivedi
IPC分类号： G01K3/00 , G01K15/00
CPC分类号： G01K3/005
摘要： A method and apparatus for adjusting clock skew involves sensing a temperature at a location on an integrated circuit. A temperature sensor indicates a temperature value of the location on the integrated circuit. The temperature value is monitored, and a tunable buffer is adjusted dependent on the monitoring. The tunable buffer is used to adjust clock skew.
摘要翻译：用于调整时钟偏移的方法和装置包括感测集成电路上的位置处的温度。温度传感器表示集成电路上的位置的温度值。监视温度值，并根据监控调整可调缓冲区。可调谐缓冲器用于调整时钟偏移。

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