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61. 发明授权

US6099705A Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer 有权
标题翻译：用于在半导体晶片上形成均匀金属层的物理气相沉积装置
公开(公告)号：US6099705A
公开(公告)日：2000-08-08
申请号：US391323
申请日：1999-09-08
申请人： Hsueh-Chung Chen , Juan-Yuan Wu , Water Lur
发明人： Hsueh-Chung Chen , Juan-Yuan Wu , Water Lur
IPC分类号： C23C14/35 , C23C14/38 , C23C14/40 , C23C14/42 , C23C14/44
CPC分类号： C23C14/35
摘要： A physical vapor deposition device comprises a vacuum chamber in which Ar ions are generated, a wafer chuck for holding a circular-shaped semiconductor wafer, a circular-shaped metal target above the wafer, an annular metal coil between the metal target and the wafer and made of the same material as the metal target, and a voltage controller for supplying voltage to the metal target, the wafer chuck and the metal coil. During a PVD processing, the voltage controller generates voltage biases between the metal target and the wafer chuck and between the metal coil and wafer chuck. That causes Ar ions to bombard the metal target to release metal atoms sputtering onto the center portion of the wafer, and causes Ar ions to bombard the metal coil to release the metal atoms sputtering onto the peripheral portion of the wafer so as to create a uniform metal layer on the wafer.
摘要翻译：物理气相沉积装置包括其中产生Ar离子的真空室，用于保持圆形半导体晶片的晶片卡盘，晶片上方的圆形金属靶，金属靶和晶片之间的环形金属线圈，以及由与金属靶相同的材料制成，以及用于向金属靶，晶片卡盘和金属线圈提供电压的电压控制器。在PVD处理期间，电压控制器在金属靶和晶片卡盘之间以及金属线圈和晶片卡盘之间产生电压偏压。这导致Ar离子轰击金属靶，释放金属原子溅射到晶片的中心部分，并导致Ar离子轰击金属线圈，以将金属原子溅射到晶片的周边部分，从而形成均匀的晶圆上的金属层。

62. 发明授权

US6093089A Apparatus for controlling uniformity of polished material 有权
标题翻译：用于控制抛光材料均匀性的装置
公开(公告)号：US6093089A
公开(公告)日：2000-07-25
申请号：US236522
申请日：1999-01-25
申请人： Hsueh-Chung Chen , Juan-Yuan Wu , Water Lur
发明人： Hsueh-Chung Chen , Juan-Yuan Wu , Water Lur
IPC分类号： B24B41/06 , B24B49/16 , B24B7/22
CPC分类号： B24B37/30 , B24B41/06 , B24B49/16
摘要： An apparatus for controlling a uniformity of a polished material is described. An air bag comprises a plurality of tubular rings. An air-bag manifold controller is connected to the tubular rings. The air-bag manifold controller controls inflation and deflation of the tubular rings in order to draw up the polished material and control pressure difference between different areas of the polished material.
摘要翻译：描述了一种用于控制抛光材料的均匀性的装置。气囊包括多个管状环。气囊歧管控制器连接到管状环。气囊歧管控制器控制管状环的膨胀和放气，以便画出抛光的材料并控制抛光材料的不同区域之间的压力差。

63. 发明授权

US08232659B2 Three dimensional IC device and alignment methods of IC device substrates 有权
标题翻译： IC器件基板的三维IC器件和对准方法
公开(公告)号：US08232659B2
公开(公告)日：2012-07-31
申请号：US12048015
申请日：2008-03-13
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
IPC分类号： H01L23/544 , H01L23/34
CPC分类号： H01L21/681
摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.
摘要翻译： IC器件基板的对准方法。第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

64. 发明申请

US20100194501A1 STRUCTURE DESIGN FOR MINIMIZING ON-CHIP INTERCONNECT INDUCTANCE 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US20100194501A1
公开(公告)日：2010-08-05
申请号：US12759836
申请日：2010-04-14
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

65. 发明授权

US07714443B2 Pad structure design with reduced density 有权
标题翻译：垫结构设计，密度降低
公开(公告)号：US07714443B2
公开(公告)日：2010-05-11
申请号：US11458501
申请日：2006-07-19
申请人： Hsien-Wei Chen , Anbiarshy Wu , Shih-Hsun Hsu , Shang-Yun Hou , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Anbiarshy Wu , Shih-Hsun Hsu , Shang-Yun Hou , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01L23/52
CPC分类号： H01L21/76895 , H01L22/34 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L2224/05093 , H01L2224/05096 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/14 , H01L2924/30105
摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.
摘要翻译：互连结构至少包括第一互连层和第二互连层。第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。第一和第二互连层的焊盘结构彼此连接。

66. 发明授权

US07705696B2 Structure design for minimizing on-chip interconnect inductance 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US07705696B2
公开(公告)日：2010-04-27
申请号：US11688903
申请日：2007-03-21
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

67. 发明授权

US07512924B2 Semiconductor device structure and methods of manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US07512924B2
公开(公告)日：2009-03-31
申请号：US11333618
申请日：2006-01-17
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.
摘要翻译：提供了一种生成半导体器件阵列布局的方法。提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

68. 发明授权

US07371663B2 Three dimensional IC device and alignment methods of IC device substrates 有权
标题翻译： IC器件基板的三维IC器件和对准方法
公开(公告)号：US07371663B2
公开(公告)日：2008-05-13
申请号：US11174511
申请日：2005-07-06
申请人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
发明人： Hsueh-Chung Chen , Chine-Gie Lou , Su-Chen Fan
IPC分类号： H01L21/00
CPC分类号： H01L21/681
摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.
摘要翻译： IC器件基板的对准方法。第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。

69. 发明申请

US20070015365A1 Method and apparatus for enhanced CMP planarization using surrounded dummy design 有权
公开(公告)号：US20070015365A1
公开(公告)日：2007-01-18
申请号：US11181433
申请日：2005-07-14
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/31053
摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

70. 发明授权

US06930038B2 Dual damascene partial gap fill polymer fabrication process 失效
公开(公告)号：US06930038B2
公开(公告)日：2005-08-16
申请号：US09863647
申请日：2001-05-23
申请人： Chingfu Lin , Hsueh-Chung Chen
发明人： Chingfu Lin , Hsueh-Chung Chen
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808
摘要： A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer. The photoresist layer and the partial fill polymer layer are then removed, to expose a part of the conductive layer. The via hole and trench are filled with metal material, to form a plug and line simultaneously.

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