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61. 发明授权

US07538025B2 Dual damascene process flow for porous low-k materials 有权
标题翻译：用于多孔低k材料的双镶嵌工艺流程
公开(公告)号：US07538025B2
公开(公告)日：2009-05-26
申请号：US10714304
申请日：2003-11-14
申请人： Chao-Cheng Chen , Chen-Nan Yeh , Chien-Chung Fu
发明人： Chao-Cheng Chen , Chen-Nan Yeh , Chien-Chung Fu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02126 , H01L21/02203 , H01L21/31695
摘要： A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.
摘要翻译：一种形成双镶嵌开口的方法，包括以下步骤。提供一种其上形成有上覆的暴露的导电层的结构。在暴露的导电层上形成电介质层。在电介质层上形成抗反射涂层。使用通孔打开工艺蚀刻抗反射层和电介质层，以形成暴露导电层的一部分的初始通孔。至少在导电层的暴露部分上形成保护膜部分。将抗反射涂层和电介质层图案化以将初始通孔减小到减小的通孔，并形成基本上位于经过还原通孔的中心的沟槽开口。沟槽开口和通孔包括双镶嵌开口。

62. 发明授权

US07029992B2 Low oxygen content photoresist stripping process for low dielectric constant materials 失效
标题翻译：低介电常数材料的低含氧光刻胶剥离工艺
公开(公告)号：US07029992B2
公开(公告)日：2006-04-18
申请号：US10920099
申请日：2004-08-17
申请人： Jyu-Horng Shieh , Yi-Nien Su , Jang-Shiang Tsai , Chen-Nan Yeh , Hun-Jan Tao
发明人： Jyu-Horng Shieh , Yi-Nien Su , Jang-Shiang Tsai , Chen-Nan Yeh , Hun-Jan Tao
IPC分类号： H01L21/322
CPC分类号： H01L21/31138 , G03F7/427
摘要： A plasma containing 5–10% oxygen and 90–95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.
摘要翻译：含有5-10％氧气和90-95％惰性气体的等离子体从形成在半导体器件上或半导体器件中的低k电介质材料上剥离光致抗蚀剂。惰性气体可以是氮气，氢气或它们的组合，或者它可以包括氮气，氢气，NH 3，Ar，He和CF 4中的至少一种。。等离子体的工作压力可以在1毫托至150毫升之间。等离子体去除光致抗蚀剂，在腐蚀性蚀刻工艺期间在光致抗蚀剂上形成的硬皮以及在蚀刻工艺期间形成的聚合物沉积。等离子体以足够高的生产用途的速率剥离光致抗蚀剂，并且不会明显地攻击含碳低k电介质材料。还提供了包括含有半导体衬底和低含氧等离子体的等离子体工具的装置。

63. 发明申请

US20060003576A1 Dual damascene trench formation to avoid low-K dielectric damage 有权
标题翻译：双镶嵌沟槽形成，以避免低K介电损伤
公开(公告)号：US20060003576A1
公开(公告)日：2006-01-05
申请号：US10882058
申请日：2004-06-30
申请人： Chen-Nan Yeh , Tsiao-Chen Wu , Chao-Cheng Chen
发明人： Chen-Nan Yeh , Tsiao-Chen Wu , Chao-Cheng Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76801 , H01L21/76808 , H01L2221/1026 , H01L2221/1031
摘要： A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.
摘要翻译：一种用于形成双镶嵌的方法，包括提供包括通孔的第一介电绝缘层; 在所述第一IMD层上形成有机介电层以包括填充所述通孔; 在有机介电层上形成硬掩模层; 光刻图案化和干蚀刻硬掩模层和有机电介质层以留下覆盖通孔开口的虚拟部分; 在所述虚拟部分上形成氧化物衬垫; 在所述氧化物衬垫上形成围绕所述虚拟部分的第二介电绝缘层; 平面化第二介电绝缘层以暴露虚设部分的上部; 并且去除有机电介质层以形成包括氧化物衬里衬里沟槽部分侧壁的双镶嵌开口。

64. 发明授权

US07510940B2 Method for fabricating dual-gate semiconductor device 有权
标题翻译：双栅半导体器件制造方法
公开(公告)号：US07510940B2
公开(公告)日：2009-03-31
申请号：US11707490
申请日：2007-02-16
申请人： Chen-Nan Yeh , Mong Song Liang , Ryan Chia-Jen Chen , Yuan-Hung Chiu
发明人： Chen-Nan Yeh , Mong Song Liang , Ryan Chia-Jen Chen , Yuan-Hung Chiu
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.
摘要翻译：一种制造双栅极半导体器件的方法。优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料，蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。

65. 发明申请

US20070004193A1 Method for reworking low-k dual damascene photo resist 审中-公开
标题翻译：低k双重镶嵌光刻胶修复方法
公开(公告)号：US20070004193A1
公开(公告)日：2007-01-04
申请号：US11173275
申请日：2005-07-01
申请人： Tsang-Jiuh Wu , Chen-Nan Yeh , Dean Li , Hui Ouyang
发明人： Tsang-Jiuh Wu , Chen-Nan Yeh , Dean Li , Hui Ouyang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A new method of forming a dual damascene structure involves forming a via-level precursor structure on a substrate and spin coating an oxide protective layer over the bottom anti-reflective coating, which is the last layer of the via-level precursor structure. A trench-level photoresist layer is deposited over the oxide protective layer to form a trench pattern etch mask. The oxide protective layer protects the BARC layer and the via plugs from photoresist removing process. When and if the trench-level photoresist layer is to be reworked, the trench-level photoresist layer is simply removed without removing the BARC layer and the via plugs under the oxide protective layer.
摘要翻译：形成双镶嵌结构的新方法包括在基底上形成通孔级前体结构，并在作为通孔级前体结构的最后一层的底部抗反射涂层上旋转涂覆氧化物保护层。沟槽级光致抗蚀剂层沉积在氧化物保护层上以形成沟槽图案蚀刻掩模。氧化物保护层保护BARC层和通孔插塞免受光致抗蚀剂的去除。当沟槽层光致抗蚀剂层要被再加工时，沟槽层光致抗蚀剂层被简单地去除，而不去除氧化物保护层下的BARC层和通孔塞。

66. 发明申请

US20080197420A1 Method for fabricating dual-gate semiconductor device 有权
标题翻译：双栅半导体器件制造方法
公开(公告)号：US20080197420A1
公开(公告)日：2008-08-21
申请号：US11707490
申请日：2007-02-16
申请人： Chen-Nan Yeh , Mong Song Liang , Ryan Chia-Jen Chen , Yuan-Hung Chiu
发明人： Chen-Nan Yeh , Mong Song Liang , Ryan Chia-Jen Chen , Yuan-Hung Chiu
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.
摘要翻译：一种制造双栅极半导体器件的方法。优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料，蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。

67. 发明授权

US07094683B2 Dual damascene method for ultra low K dielectrics 有权
标题翻译：用于超低K电介质的双镶嵌方法
公开(公告)号：US07094683B2
公开(公告)日：2006-08-22
申请号：US10633909
申请日：2003-08-04
申请人： Chen-Nan Yeh , Yung-Cheng Lu
发明人： Chen-Nan Yeh , Yung-Cheng Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76804
摘要： A method for forming a dual damascene opening to protect a low-K dielectric insulating layer including providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer; depositing a first dielectric layer stack layer comprising at least one dielectric insulating layer over the at least one dielectric insulating to seal the via opening; blanket depositing a second dielectric layer stack comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack; photolithographically patterning and etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed; and, etching through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.
摘要翻译：一种用于形成双镶嵌开口以保护低K介电绝缘层的方法，包括提供半导体工艺晶片，其包括通过至少一个介电绝缘层的厚度部分延伸的通孔; 在所述至少一个电介质绝缘体上沉积包括至少一个介电绝缘层的第一介电层堆叠层，以密封所述通孔开口; 包覆沉积包括至少一个电介质层的第二介电层堆叠，以在第一介电层堆叠之上形成硬掩模，并与第一介电层堆叠接触; 通过硬掩模和第一介电层堆叠的厚度进行光刻图案化和蚀刻，以形成覆盖并包围通孔孔的沟槽开口蚀刻图案，同时使通孔开口密封; 并且蚀刻穿过所述至少一个介电绝缘层的厚度部分以形成双镶嵌开口。

68. 发明申请

US20060040474A1 LOW OXYGEN CONTENT PHOTORESIST STRIPPING PROCESS FOR LOW DIELECTRIC CONSTANT MATERIALS 失效
标题翻译：低介电常数材料的低氧含量光电子剥离工艺
公开(公告)号：US20060040474A1
公开(公告)日：2006-02-23
申请号：US10920099
申请日：2004-08-17
申请人： Jyu-Horng Shieh , Yi-Nien Su , Jang-Shiang Tsai , Chen-Nan Yeh , Hun-Jan Tao
发明人： Jyu-Horng Shieh , Yi-Nien Su , Jang-Shiang Tsai , Chen-Nan Yeh , Hun-Jan Tao
IPC分类号： H01L21/322
CPC分类号： H01L21/31138 , G03F7/427
摘要： A plasma containing 5-10% oxygen and 90-95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.
摘要翻译：含有5-10％氧气和90-95％惰性气体的等离子体从形成在半导体器件上或半导体器件中的低k电介质材料上剥离光致抗蚀剂。惰性气体可以是氮气，氢气或它们的组合，或者它可以包括氮气，氢气，NH 3，Ar，He和CF 4中的至少一种。。等离子体的工作压力可以在1毫托至150毫升之间。等离子体去除光致抗蚀剂，在腐蚀性蚀刻工艺期间在光致抗蚀剂上形成的硬皮以及在蚀刻工艺期间形成的聚合物沉积。等离子体以足够高的生产用途的速率剥离光致抗蚀剂，并且不会明显地攻击含碳低k电介质材料。还提供了包括含有半导体衬底和低含氧等离子体的等离子体工具的装置。

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