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61. 发明授权

US07323737B2 DRAM constructions and electronic systems 有权
标题翻译： DRAM结构和电子系统
公开(公告)号：US07323737B2
公开(公告)日：2008-01-29
申请号：US11517209
申请日：2006-09-06
申请人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
发明人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
IPC分类号： H01L27/108 , H01L23/48 , H01L21/8234
CPC分类号： H01L27/10855 , H01L27/10852 , H01L28/40 , H01L28/57
摘要： The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.
摘要翻译：本发明包括其中金属氧化物电介质材料沉积在阻挡层上的方法。阻挡层可以包括金属和碳，硼和氮中的一种或多种的组合物，并且介电材料的金属氧化物可以包含与阻挡层相同的金属。电介质材料/阻挡层结构可以结合到电容器中。电容器可以用在例如DRAM单元中，DRAM单元又可以用在电子系统中。

62. 发明授权

US07303991B2 Atomic layer deposition methods 有权
标题翻译：原子层沉积法
公开(公告)号：US07303991B2
公开(公告)日：2007-12-04
申请号：US10863048
申请日：2004-06-07
申请人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
发明人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
IPC分类号： H01L21/44
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
摘要翻译：本发明包括在基板上形成沉积的组合物层的原子层沉积方法。该方法包括将半导体衬底定位在原子层沉积室内。在基材上形成中间体组合物单层，随后是与中间体组合物反应所需的沉积组合物，共同地将多个不同的组合物沉积前体流入沉积室内的基底。材料粘附到室内部件表面，从而依次形成。在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中并且有效地与这种粘附材料反应的室。在反应气体流动之后，重复这种顺序形成。考虑进一步的实现。

63. 发明授权

US07271077B2 Deposition methods with time spaced and time abutting precursor pulses 有权
标题翻译：具有时间间隔和时间邻接前体脉冲的沉积方法
公开(公告)号：US07271077B2
公开(公告)日：2007-09-18
申请号：US10734999
申请日：2003-12-12
申请人： Eugene Marsh , Brian Vaartstra , Paul J. Castrovillo , Cem Basceri , Garo J. Derderian , Gurtej S. Sandhu
发明人： Eugene Marsh , Brian Vaartstra , Paul J. Castrovillo , Cem Basceri , Garo J. Derderian , Gurtej S. Sandhu
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： C30B25/14 , C23C16/45527 , C30B25/02
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。第一前体气体流动包括多个第一前体气体脉冲。多个第一前体气体脉冲包括当没有气体被供给到腔室时在两个紧邻的第一前体气体脉冲之间的至少一个总时间段。在衬底上形成第一单层之后，组成不同于第一衬底的第二前体气体流入沉积室内的衬底，有效地在第一单层上形成第二单层。考虑了其他方面和实现。

64. 发明授权

US07268388B2 One-transistor composite-gate memory 有权
标题翻译：单晶体管复合栅极存储器
公开(公告)号：US07268388B2
公开(公告)日：2007-09-11
申请号：US10926675
申请日：2004-08-26
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C8/12 , G11C16/0416 , G11C16/0466 , H01L29/513 , H01L29/792
摘要： One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
摘要翻译：单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

65. 发明授权

US07253085B2 Deposition methods 有权
标题翻译：沉积方法
公开(公告)号：US07253085B2
公开(公告)日：2007-08-07
申请号：US11326739
申请日：2006-01-05
申请人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
发明人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
IPC分类号： H01L21/36 , C30B21/20
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.
摘要翻译：本发明包括半导体材料的选择性沉积方法。将基板放置在反应室内。基板包括第一表面和第二表面。第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比在第一个表面。进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

66. 发明授权

US07033642B2 Plasma enhanced chemical vapor deposition method of forming a titanium silicide comprising layer 有权
标题翻译：形成层状硅化钛的等离子体增强化学气相沉积法
公开(公告)号：US07033642B2
公开(公告)日：2006-04-25
申请号：US10666025
申请日：2003-09-17
申请人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip H. Campbell , Gurtej S. Sandhu
发明人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip H. Campbell , Gurtej S. Sandhu
IPC分类号： C23C16/14 , C23C16/24
CPC分类号： H01L21/28518 , C23C16/42 , H01L21/28556
摘要： Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.
摘要翻译：公开了在衬底上形成包括层的硅化钛的化学气相沉积方法。 TiCl 4 S和至少一种硅烷首先以等于或高于TiCl 4的第一体积比与硅烷一起进料到室中，持续第一段时间。该比例足够高以避免钛硅化物在衬底上的可测量沉积。或者，在第一时间段内没有可测量的硅烷进料到室中。无论如何，在第一阶段之后，将TiCl 4 S和至少一种硅烷以等于或低于TiCl 4的第二体积比与硅烷一起进料到室中，持续第二阶段时间。如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。无论如何，第二次进料对于等离子体有效地提高了化学气相沉积在基底上的包含硅的硅化钛。

67. 发明授权

US06896730B2 Atomic layer deposition apparatus and methods 失效
标题翻译：原子层沉积装置及方法
公开(公告)号：US06896730B2
公开(公告)日：2005-05-24
申请号：US10163689
申请日：2002-06-05
申请人： Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , Demetrius Sarigiannis
发明人： Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , Demetrius Sarigiannis
IPC分类号： C30B25/00 , C30B35/00 , C30B25/14 , C30B25/16
CPC分类号： C30B35/00 , C30B25/00 , C30B29/68
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A fixed volume first precursor gas charge is provided within a gas flow path to the deposition chamber. A fixed volume purge gas charge is provided within the gas flow path serially upstream of the first precursor gas charge. The first precursor gas charge and the purge gas charge are serially flowed along the gas flow path to the substrate within the deposition chamber effective to form a monolayer on the substrate and purge at least some of the first precursor gas from the substrate. Apparatus are also disclosed.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。在到达沉积室的气体流动路径内提供固定体积的第一前体气体进料。在第一前体气体装料的串联的气体流动路径内提供固定体积的吹扫气体装料。第一前体气体装料和吹扫气体装料沿着气体流动路径顺序地流动到沉积室内的基板，有效地在基板上形成单层，并且从基板吹扫至少一些第一前体气体。还公开了装置。

68. 发明授权

US06730355B2 Chemical vapor deposition method of forming a material over at least two substrates 失效
标题翻译：在至少两个基材上形成材料的化学气相沉积方法
公开(公告)号：US06730355B2
公开(公告)日：2004-05-04
申请号：US10094579
申请日：2002-03-06
申请人： Ammar Derraa , Cem Basceri , Irina Vasilyeva , Philip H. Campbell , Gurtej S. Sandhu
发明人： Ammar Derraa , Cem Basceri , Irina Vasilyeva , Philip H. Campbell , Gurtej S. Sandhu
IPC分类号： C23C1642
CPC分类号： C23C16/4408 , C23C16/42 , C23C16/4405
摘要： A first substrate is provided within a chemical vapor deposition chamber. A reactive gas mixture comprising TiCl4 and a silane is provided within the chamber effective to first chemically vapor deposit a titanium silicide comprising layer on the first substrate. After the first deposit, the first substrate is removed from the chamber. After the first deposit, a first cleaning is conducted within the chamber with a chlorine comprising gas. After the first cleaning, a second cleaning is conducted within the chamber with a hydrogen comprising gas. After the second cleaning and after the removing, a titanium silicide comprising layer is chemically vapor deposited over a second substrate within the chamber using a reactive gas mixture comprising TiCl4 and a silane. Other implementations are disclosed.
摘要翻译：第一基板设置在化学气相沉积室内。在室内提供包含TiCl 4和硅烷的反应气体混合物，其有效地首先在第一衬底上化学气相沉积包含硅化钛的层。在第一次沉积之后，将第一衬底从腔室中取出。在第一次沉积之后，在室内用含氯气体进行第一次清洗。在第一次清洁之后，在室内用含氢气体进行第二次清洗。在第二次清洁之后并且在除去之后，使用包含TiCl 4和硅烷的反应性气体混合物，在室内的第二衬底上化学气相沉积包含硅化钛的层。公开了其他实现。

69. 发明授权

US06649466B2 Method of forming DRAM circuitry 失效
标题翻译：形成DRAM电路的方法
公开(公告)号：US06649466B2
公开(公告)日：2003-11-18
申请号：US10243385
申请日：2002-09-13
申请人： Cem Basceri , Garo J. Derderian , M. R. Visokay , J. M. Drynan , Gurtej S. Sandhu
发明人： Cem Basceri , Garo J. Derderian , M. R. Visokay , J. M. Drynan , Gurtej S. Sandhu
IPC分类号： H01L218242
CPC分类号： H01L21/31122 , H01L21/28061 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/31604 , H01L21/32051 , H01L27/10811 , H01L27/10888 , H01L28/90 , H01L29/6659
摘要： In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate. In one implementation, the layer is exposed to WF6 under conditions effective to both etch substantially amorphous Ta2O5 from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.
摘要翻译：部分地，公开了半导体处理方法，在衬底上沉积含钨层的方法，在衬底上沉积含氮化钨的层的方法，在衬底上沉积包含硅化钨的层的方法，形成晶体管栅极的方法在衬底上划线，形成图案化的基本上结晶的Ta 2 O 5的材料的方法，以及形成包含基本上结晶的Ta 2 O 5的材料的电容器电介质区域的方法。在一个实施方案中，半导体处理方法包括在半导体衬底上形成包含基本非晶态的Ta 2 O 5层。该层在有效从底物上蚀刻基本无定形Ta 2 O 5的条件下暴露于WF6。在一个实施方案中，该层在有效地从衬底上蚀刻基本上无定形Ta 2 O 5的条件下暴露于WF6，并在曝光期间在衬底上沉积含钨层。

70. 发明授权

US06337237B1 Capacitor processing method and DRAM processing method 失效
标题翻译：电容处理方法和DRAM处理方法
公开(公告)号：US06337237B1
公开(公告)日：2002-01-08
申请号：US09388827
申请日：1999-09-01
申请人： Cem Basceri , Gurtej S. Sandhu
发明人： Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L218242
CPC分类号： H01L28/55
摘要： A capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface. In one implementation, a DRAM processing method includes forming DRAM circuitry comprising DRAM array capacitors having a common cell electrode, respective storage node electrodes, and a high k capacitor dielectric region therebetween. A voltage is applied to at least one of the first and second electrodes to produce a voltage differential therebetween under conditions effective to cause oxygen vacancies in the high k capacitor dielectric region to migrate toward one of the cell electrode or the respective storage node electrodes and react with oxygen to fill at least a portion of the oxygen vacancies in the capacitor dielectric region.
摘要翻译：电容器处理方法包括形成电容器，该电容器包括在其间具有电容器电介质区域的第一和第二电极。第一电极在第一界面处与电容器介电区域接合。第二电极在第二界面处与电容器介电区域接合。电容器电介质区域中具有多个氧空位。在形成电容器之后，电场被施加到电容器电介质区域，以引起氧空位向第一和第二界面之一迁移。氧原子优选设置在有效填充电容器电介质区域中的氧空位的至少一部分的一个界面处。优选地，高k电容器介电区域中的氧空位的至少一部分由包括最靠近一个界面的第一或第二电极的氧化物材料填充。在一个实现中，DRAM处理方法包括形成DRAM电路，其包括DRAM阵列电容器，其具有公共单元电极，各自的存储节点电极和它们之间的高k电容器电介质区域。电压施加到第一和第二电极中的至少一个，以在有效地引起高k电容器介电区域中的氧空位迁移到电池电极或相应存储节点电极之一的条件下产生它们之间的电压差，并且反应用氧气填充电容器介质区域中的氧空位的至少一部分。

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