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61. 发明授权

US09294135B2 Digital radio frequency (RF) receiver 有权
标题翻译：数字射频（RF）接收机
公开(公告)号：US09294135B2
公开(公告)日：2016-03-22
申请号：US13609638
申请日：2012-09-11
申请人： Ik Soo Eo , Sang-Kyun Kim , Mun Yang Park , Seon-Ho Han , Hyun Kyu Yu
发明人： Ik Soo Eo , Sang-Kyun Kim , Mun Yang Park , Seon-Ho Han , Hyun Kyu Yu
IPC分类号： H04B1/00
CPC分类号： H04B1/0021
摘要： A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.
摘要翻译：数字RF接收机根据用于多模式接收，MIMO接收和带宽扩展接收的模式和频带不使用单独的接收机，并且仅改变单个接收机结构中的设置变量以便实现多模式接收， MIMO接收，带宽扩展接收和/或同时多模式操作，从而可以减少接收机的复杂性，开发成本和功耗。

62. 发明授权

US09276800B2 Single frequency synthesizer based FDD transceiver 有权
标题翻译：基于单频合成器的FDD收发器
公开(公告)号：US09276800B2
公开(公告)日：2016-03-01
申请号：US13608677
申请日：2012-09-10
申请人： Hyun Ho Boo , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
发明人： Hyun Ho Boo , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
IPC分类号： H04J1/02 , H04L27/38 , H04L27/20 , H04L27/233 , H04L27/36 , H04B1/00
CPC分类号： H04L27/3836 , H04B1/0007 , H04L27/206 , H04L27/2092 , H04L27/2332 , H04L27/362 , H04L27/3854
摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.
摘要翻译：本发明涉及一种基于单频合成器的FDD收发器。单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

63. 发明授权

US08471739B2 Digital analog converter and method for calibrating sources thereof 失效
标题翻译：数字模拟转换器及其源的校准方法
公开(公告)号：US08471739B2
公开(公告)日：2013-06-25
申请号：US13312449
申请日：2011-12-06
申请人： Jang Hong Choi , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Kyu Yu
IPC分类号： H03M1/10
CPC分类号： H03M1/0653 , H03M1/685 , H03M1/747
摘要： Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.
摘要翻译：提供了一种数字模拟转换器，其根据映射表输出对数字输入值具有不同幅度的电流。数字模拟转换器包括：多个电流源; 以及校准单元，被配置为根据当前源的当前幅度对用于识别多个电流源的索引值进行排序，将关于分选的索引值的中心的左右对称的两个电流源耦合，并且将当前源成对映射表。

64. 发明授权

US08295405B2 Apparatus and method for I/Q mismatch calibration 有权
标题翻译：用于I / Q不匹配校准的装置和方法
公开(公告)号：US08295405B2
公开(公告)日：2012-10-23
申请号：US12629018
申请日：2009-12-01
申请人： Hyun Kyu Yu , Mun Yang Park , Jae Hoon Shim
发明人： Hyun Kyu Yu , Mun Yang Park , Jae Hoon Shim
IPC分类号： H04L27/22
CPC分类号： H04L27/3863
摘要： There is provided an apparatus and method for In-phase/Quadrature-phase (I/Q) mismatch calibration. The apparatus includes: a symmetrical point extracting part receiving continuous wave signals and extracting an I/Q channel average locus of the continuous wave signals; an error extracting part extracting a degree of distortion of the continuous wave signals from the extracted I/Q channel average locus; and a calibrating part calibrating a mismatch between I-channel signals and Q-channel signals of the continuous wave signals using the degree of distortion of the continuous wave signals.
摘要翻译：提供了用于同相/正交相（I / Q）不匹配校准的装置和方法。该装置包括：对称点提取部分，接收连续波信号并提取连续波信号的I / Q信道平均轨迹; 从所提取的I / Q通道平均轨迹提取连续波信号的失真程度的误差提取部分; 以及使用连续波信号的失真程度来校准连续波信号的I信道信号和Q信道信号之间的失配的校准部分。

65. 发明授权

US08274420B2 Successive approximation analog-to-digital converter 有权
标题翻译：逐次近似模数转换器
公开(公告)号：US08274420B2
公开(公告)日：2012-09-25
申请号：US12970861
申请日：2010-12-16
申请人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
发明人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/827
摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.
摘要翻译：提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

66. 发明申请

US20120161832A1 FRACTIONAL DIGITAL PLL WITH ANALOG PHASE ERROR COMPENSATOR 有权
标题翻译：具有模拟相位误差补偿器的数字数字锁相环
公开(公告)号：US20120161832A1
公开(公告)日：2012-06-28
申请号：US13310581
申请日：2011-12-02
申请人： Ja Yol Lee , Seong-Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong-Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03L7/085 , H03L2207/50
摘要： Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.
摘要翻译：公开了具有模拟相位误差补偿器的分数字数字锁相环。具有模拟相位误差补偿器的数字锁相环可以通过模拟相位误差补偿器进行分数相位误差检测和补偿，从而降低功耗，功耗噪声和瞬态电流噪声，同时提高相位误差检测分辨率。

67. 发明申请

US20120146852A1 PULSE RADAR RECEIVER 有权
标题翻译：脉冲雷达接收器
公开(公告)号：US20120146852A1
公开(公告)日：2012-06-14
申请号：US13316381
申请日：2011-12-09
申请人： Pil Jae Park , Seong Do Kim , Sung Chul Woo , Hyun Kyu Yu
发明人： Pil Jae Park , Seong Do Kim , Sung Chul Woo , Hyun Kyu Yu
IPC分类号： G01S7/285
CPC分类号： G01S7/292
摘要： A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.
摘要翻译：脉冲雷达接收机包括：功率分配器，被配置为分离用于产生TX脉冲的发射（TX）触发信号;配置为接收分频比的锁相环（PLL）和由功率分配器分离的TX触发信号;以及产生采样频率，并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。因此，通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波，可以提供高距离分辨率。因此，可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。因此，脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。

68. 发明授权

US08060020B2 Apparatus and method for removing interference signal using selective frequency phase converter 有权
标题翻译：使用选择性频率相位转换器去除干扰信号的装置和方法
公开(公告)号：US08060020B2
公开(公告)日：2011-11-15
申请号：US12628684
申请日：2009-12-01
申请人： Seong Do Kim , Ja Yol Lee , Jae Hoon Shim , Hyun Kyu Yu
发明人： Seong Do Kim , Ja Yol Lee , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H04B1/00
CPC分类号： H04B1/123
摘要： An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180° from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180° from each other.
摘要翻译：公开了一种使用选择性频率相位变换器去除干扰信号的装置和方法。使用选择性频率相位变换器去除干扰信号的装置包括：第一相位转换器，被配置为将接收的RF信号的相位转换为差分地输出具有彼此相差180°的第一和第二信号; 第二相转换器，被配置为接收第一信号并选择性地转换特定频带的相位; 配置为接收所述第二信号并选择性地转换特定频带的相位的第三相位转换器; 定时控制器，被配置为校正来自第二相位转换器的输出和第三相位转换器的输出之间的信号延迟时间; 以及加法器，被配置为将来自第二相位转换器的输出和来自第三相位转换器的输出相加，其中第二和第三相位转换器对第一和第二信号进行相位转换，使得特定频带的信号的相位做彼此之间没有180°的相位差。

69. 发明授权

US07994851B2 PSK demodulator using time-to-digital converter 失效
标题翻译： PSK解调器采用时间 - 数字转换器
公开(公告)号：US07994851B2
公开(公告)日：2011-08-09
申请号：US12511323
申请日：2009-07-29
申请人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
发明人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H04L27/06 , H03D3/18
CPC分类号： H04L27/233 , H04L27/2338
摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.
摘要翻译：使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。可以降低功耗并简化电路实现。

70. 发明授权

US07973368B2 Semiconductor device with T-gate electrode 失效
标题翻译：具有T型栅电极的半导体器件
公开(公告)号：US07973368B2
公开(公告)日：2011-07-05
申请号：US12122982
申请日：2008-05-19
申请人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hae Cheon Kim , Hyun Kyu Yu
发明人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/778 , H01L29/20 , H01L29/42316 , H01L29/66462
摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.
摘要翻译：提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

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