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61. 发明授权

US07149072B2 Multilayered chip capacitor array 有权
标题翻译：多层片式电容阵列
公开(公告)号：US07149072B2
公开(公告)日：2006-12-12
申请号：US11264486
申请日：2005-11-01
申请人： Byoung Hwa Lee , Hiroki Sato , Chang Hoon Shim , Sang Soo Park , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Seung Heon Han
发明人： Byoung Hwa Lee , Hiroki Sato , Chang Hoon Shim , Sang Soo Park , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Seung Heon Han
IPC分类号： H01G4/236 , H01G4/20
CPC分类号： H05K1/0231 , H01G2/065 , H01G4/228 , H01G4/30 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16235 , H01L2924/00014 , H01L2924/15159 , H01L2924/19041 , H01L2924/19106 , H05K2201/10515 , H05K2201/1053 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.
摘要翻译：这里公开了一种多层片状电容器阵列，其包括具有多个电介质层的电容器主体，多对第一和第二内部电极，形成在多个电介质层上，使得一对内部电极的一个电极面一对内电极的另一个电极与介于其间的多个电介质层中的一个介于其间，至少一个第一外端子和多个第二外端子形成在第一外端子的顶表面和底表面的至少一个表面上电容器本体，以及至少一个第一导电通孔和多个第二导电通孔，其形成在电容器主体的堆叠方向上，分别连接到第一外部端子和第二外部端子。

62. 发明授权

US07092236B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07092236B2
公开(公告)日：2006-08-15
申请号：US11068825
申请日：2005-03-02
申请人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/06 , H01G4/005 , H01G4/228
CPC分类号： H01G4/30 , H01G4/232
摘要： A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.
摘要翻译：一种多层片状电容器，其减少由于电流流过外部电极而产生的ESL，并确保改进的机械强度。多层片状电容器包括上虚拟层和下虚拟层; 插入在上下虚拟层之间的多个内部电极; 以及连接到内部电极的外部电极，其中下部虚拟层的厚度小于上部虚拟层的厚度。

63. 发明授权

US08681475B2 Mounting structure of circuit board having multi-layered ceramic capacitor thereon 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US08681475B2
公开(公告)日：2014-03-25
申请号：US13590270
申请日：2012-08-21
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/06
CPC分类号： H01G4/12 , H01G4/228 , H01G4/30
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构，其中层叠有电介质片的多层陶瓷电容器和形成在其两端的外部端子电极，其上形成有内部电极的电介质片，以及外部端子电极与内部电极并联连接，其中内部电极被设置为与电路板平行，外部端子电极通过导电材料接合到电路板的焊盘，并且接合高度 Ts）低于多层陶瓷电容器的电路板和底面之间的间隙（Ta）和多层陶瓷电容器的下表面的覆盖层的厚度（Tc）之和，层状陶瓷电容器，从而可以大大降低振动噪声。

64. 发明申请

US20120298407A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING MULTI-LAYERED CERAMIC CAPACITOR THEREON 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US20120298407A1
公开(公告)日：2012-11-29
申请号：US13481348
申请日：2012-05-25
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/16
CPC分类号： H05K1/111 , H01G4/12 , H01G4/30 , H05K3/3442 , H05K2201/10015 , H05K2201/2045 , Y02P70/611 , Y02P70/613
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

65. 发明申请

US20120152604A1 MOUNTING STRUCTURE OF CIRCUIT BOARD HAVING THEREON MULTI-LAYERED CERAMIC CAPACITOR, METHOD THEREOF, LAND PATTERN OF CIRCUIT BOARD FOR THE SAME, PACKING UNIT FOR MULTI-LAYERED CERAMIC CAPACITOR TAPED HORIZONTALLY AND ALIGNING METHOD THEREOF 审中-公开
标题翻译：具有多层陶瓷电容器的电路板的安装结构，其方法，电路板的土地图案，多层陶瓷电容器的包装单元和水平方法
公开(公告)号：US20120152604A1
公开(公告)日：2012-06-21
申请号：US13331619
申请日：2011-12-20
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/18 , H05K3/00 , H01G4/30
CPC分类号： H01G2/065 , H01G4/232 , H01G4/30 , H05K3/3442 , H05K13/022 , H05K2201/10015 , H05K2203/166 , Y02P70/613 , Y10T29/49124
摘要： The present invention provides a method of mounting a circuit board having thereon a multi-layered ceramic capacitor and a land pattern of a circuit board for the same. The method of mounting a circuit board having thereon a multi-layered ceramic capacitor on which a plurality of dielectric sheet having internal electrodes formed thereon are stacked and the external terminal electrodes connected to the internal electrodes in parallel are formed on both ends thereof includes conductively connecting lands of a circuit board to the external terminal electrodes in such a way that internal electrode layers of the multi-layered ceramic capacitor and the circuit board are arranged in a horizontal direction, wherein a height TS of conductive material to conductively connect the external terminal electrodes to the lands is less than ⅓ of a thickness TMLCC of the multi-layered ceramic capacitor.
摘要翻译：本发明提供了一种安装电路板的方法，其上具有多层陶瓷电容器和用于其的电路板的焊盘图案。在其上堆叠有多层陶瓷电容器的电路板的方法，其上形成有形成有内部电极的多个电介质层，并且在其两端形成有与内部电极并联连接的外部端子电极的方法包括导电连接电路板的接地部分以外部端子电极的方式使多层陶瓷电容器和电路板的内部电极层沿水平方向排列，其中导电材料的高度TS导电连接外部端子电极到土地的厚度小于多层陶瓷电容器的厚度TMLCC的1/3。

66. 发明授权

US07262952B2 Multilayer chip capacitor 失效
标题翻译：多层片式电容器
公开(公告)号：US07262952B2
公开(公告)日：2007-08-28
申请号：US11453880
申请日：2006-06-16
申请人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/232
摘要： The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.
摘要翻译：本发明提供了一种减少ESL的多层片式电容器。电容器本体具有沿厚度方向堆叠的多个电介质层。多个第一和第二内部电极通过电容器体内的电介质层彼此分离。每个第一内部电极与每个第二内部电极相对。第一和第二内部电极中的每一个包括朝向电容器主体的任何一侧延伸的至少两个引线。此外，多个外部电极形成在电容器主体的外表面上并经由引线连接到内部电极。此外，具有相同极性的垂直相邻的引线以预定角度在不同方向上延伸。第一和第二内部电极的引线设置成与第二内部电极的引线相邻并与其交替。

67. 发明授权

US09148955B2 Mounting structure of circuit board having multi-layered ceramic capacitor thereon 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US09148955B2
公开(公告)日：2015-09-29
申请号：US13481348
申请日：2012-05-25
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/18 , H05K1/11 , H05K3/34
CPC分类号： H05K1/111 , H01G4/12 , H01G4/30 , H05K3/3442 , H05K2201/10015 , H05K2201/2045 , Y02P70/611 , Y02P70/613
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

68. 发明授权

US08630083B2 Multi-layered capacitor and manufacturing method thereof 有权
标题翻译：多层电容器及其制造方法
公开(公告)号：US08630083B2
公开(公告)日：2014-01-14
申请号：US13447692
申请日：2012-04-16
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/232 , H01G4/12 , H01G4/30 , H01G4/35
摘要： A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.
摘要翻译：多层电容器包括电容器元件，其中多个电介质层是多层的，并且包括交替地形成在多个电介质层的相邻电介质层上的第一内电极和第二内电极，第一外部电极和第二外部电极，分别形成在电容器元件的外表面上以与第一内部电极和第二内部电极电连接;变形抑制电极，形成在电容器的外表面上并且与第一外部电极和第二外部电极分离以与第一内部电极和第二内部电极电隔离。

69. 发明申请

US20130155574A1 MULTILAYER CERAMIC ELECTRONIC COMPONENT 审中-公开
标题翻译：多层陶瓷电子元件
公开(公告)号：US20130155574A1
公开(公告)日：2013-06-20
申请号：US13541494
申请日：2012-07-03
申请人： Min Cheol PARK , Byoung Hwa Lee , Dong Seok Park , Young Ghyu Ahn , Sang Soo Park
发明人： Min Cheol PARK , Byoung Hwa Lee , Dong Seok Park , Young Ghyu Ahn , Sang Soo Park
IPC分类号： H01G4/012
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： A multilayer ceramic electronic component having high reliability by reducing equivalent series resistance (ESR) dispersion is provided. Connectivity between internal electrodes and external electrodes is secured by introducing dummy electrodes connected to first and second terminal electrodes, to third and fourth internal electrode layers. ESR dispersion of the multilayer ceramic electronic component is reduced to obtain high reliability.
摘要翻译：提供了通过降低等效串联电阻（ESR）色散而具有高可靠性的多层陶瓷电子元件。通过将连接到第一和第二端子电极的虚设电极引入第三和第四内部电极层来确保内部电极和外部电极之间的连通性。降低多层陶瓷电子部件的ESR分散，获得高可靠性。

70. 发明申请

US20120275081A1 MULTI-LAYERED CAPACITOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：多层电容器及其制造方法
公开(公告)号：US20120275081A1
公开(公告)日：2012-11-01
申请号：US13447692
申请日：2012-04-16
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/30
CPC分类号： H01G4/232 , H01G4/12 , H01G4/30 , H01G4/35
摘要： A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.
摘要翻译：多层电容器包括电容器元件，其中多个电介质层是多层的，并且包括交替地形成在多个电介质层的相邻电介质层上的第一内电极和第二内电极，第一外部电极和第二外部电极，分别形成在电容器元件的外表面上以与第一内部电极和第二内部电极电连接;变形抑制电极，形成在电容器的外表面上并且与第一外部电极和第二外部电极分离以与第一内部电极和第二内部电极电隔离。

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