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61. 发明授权

US07005670B2 Thin film transistor array substrate for liquid crystal display and method of fabricating the same 失效
标题翻译：用于液晶显示器的薄膜晶体管阵列基板及其制造方法
公开(公告)号：US07005670B2
公开(公告)日：2006-02-28
申请号：US11167155
申请日：2005-06-28
申请人： Sang-Gab Kim , Mun-Pyo Hong
发明人： Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/06 , H01L27/01
CPC分类号： H01L29/66765 , G02F2001/13629 , H01L27/124 , H01L29/456 , H01L29/4908
摘要： In a method of fabricating a thin film transistor array substrate, an aluminum-based conductive layer is deposited onto an insulating substrate, and patterned to form a gate line assembly. The gate line assembly includes gate lines, gate electrodes, and gate pads. A gate insulating layer is formed on the substrate with the gate line assembly. A semiconductor layer, and an ohmic contact layer are sequentially formed on the gate insulating layer. A double-layered conductive film with a chrome-based under-layer and an aluminum-based over-layer is deposited onto the substrate, and patterned to form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. The chrome-based under-layer of the conductive film is patterned through dry etching while using Cl2 or HCl as the dry etching gas. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. Indium zinc oxide is deposited onto the substrate, and patterned to thereby form pixel electrodes connected to the drain electrodes through the corresponding contact holes, and subsidiary gate and data pads connected to the gate and data pads through the corresponding contact holes.
摘要翻译：在制造薄膜晶体管阵列基板的方法中，将铝基导电层沉积到绝缘基板上，并被图案化以形成栅极线组件。栅极线组件包括栅极线，栅电极和栅极焊盘。在栅极线组件的基板上形成栅极绝缘层。半导体层和欧姆接触层依次形成在栅绝缘层上。将具有铬基底层和铝基超层的双层导电膜沉积到衬底上，并被图案化以形成数据线组件。数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。通过干蚀刻将导电膜的铬基底层图案化，同时使用Cl 2/2或HCl作为干蚀刻气体。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。将铟锌氧化物沉积在衬底上，并被图案化，从而通过相应的接触孔形成连接到漏电极的像素电极，以及通过对应的接触孔连接到栅极和数据焊盘的辅助栅极和数据焊盘。

62. 发明申请

US20050201508A1 Shift register and display device including the same 有权
标题翻译：移位寄存器和显示设备包括相同
公开(公告)号：US20050201508A1
公开(公告)日：2005-09-15
申请号：US11078985
申请日：2005-03-11
申请人： Kyong-Ju Shin , Chong-Chul Chae , Mun-Pyo Hong , Cheol-Woo Park , Nam-Seok Roh
发明人： Kyong-Ju Shin , Chong-Chul Chae , Mun-Pyo Hong , Cheol-Woo Park , Nam-Seok Roh
IPC分类号： G09G3/36 , G06M11/02
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G09G2320/0223 , G09G2320/041 , G09G2330/021 , G11C19/28
摘要： A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage includes a set terminal, a reset terminal, a clock terminal, and first and second output terminals.
摘要翻译：移位寄存器包括彼此连接的级，其中每一级根据时钟信号中的任何一个和两个不同级中的每一个的输出产生输出信号。每个时钟信号具有小于50％的占空比和与每个其它时钟信号不同的相位。显示装置包括像素，信号线，以及第一和第二移位寄存器，每个移位寄存器各自具有彼此连接的级并且向信号线产生输出信号。每个级包括设置终端，复位终端，时钟终端以及第一和第二输出端。

63. 发明授权

US06943367B2 Thin film transistor array panel 失效
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US06943367B2
公开(公告)日：2005-09-13
申请号：US10395233
申请日：2003-03-25
申请人： Sang-Gab Kim , Mun-Pyo Hong
发明人： Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： G02F1/1368 , G02F1/136 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/768 , H01L21/77 , H01L21/84 , H01L23/52 , H01L27/12 , H01L29/45 , H01L29/49 , H01L29/786 , H01L29/06 , H01L27/01
CPC分类号： H01L29/66765 , G02F2001/13629 , H01L27/124 , H01L29/456 , H01L29/4908
摘要： In a method of fabricating a thin film transistor array substrate, an aluminum-based conductive layer is deposited onto an insulating substrate, and patterned to form a gate line assembly. The gate line assembly includes gate lines, gate electrodes, and gate pads. A gate insulating layer is formed on the substrate with the gate line assembly. A semiconductor layer, and an ohmic contact layer are sequentially formed on the gate insulating layer. A double-layered conductive film with a chrome-based under-layer and an aluminum-based over-layer is deposited onto the substrate, and patterned to form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. The chrome-based under-layer of the conductive film is patterned through dry etching while using Cl2 or HCl as the dry etching gas. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. Indium zinc oxide is deposited onto the substrate, and patterned to thereby form pixel electrodes connected to the drain electrodes through the corresponding contact holes, and subsidiary gate and data pads connected to the gate and data pads through the corresponding contact holes.
摘要翻译：在制造薄膜晶体管阵列基板的方法中，将铝基导电层沉积到绝缘基板上，并被图案化以形成栅极线组件。栅极线组件包括栅极线，栅电极和栅极焊盘。在栅极线组件的基板上形成栅极绝缘层。半导体层和欧姆接触层依次形成在栅绝缘层上。将具有铬基底层和铝基超层的双层导电膜沉积到衬底上，并被图案化以形成数据线组件。数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。通过干蚀刻将导电膜的铬基底层图案化，同时使用Cl 2/2或HCl作为干蚀刻气体。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。将铟锌氧化物沉积在衬底上，并被图案化，从而通过相应的接触孔形成连接到漏电极的像素电极，以及通过对应的接触孔连接到栅极和数据焊盘的辅助栅极和数据焊盘。

64. 发明授权

US06850294B2 Liquid crystal display 有权
标题翻译：液晶显示器
公开(公告)号：US06850294B2
公开(公告)日：2005-02-01
申请号：US10469848
申请日：2002-02-25
申请人： Nam-Seok Roh , Mun-Pyo Hong , Chong-Chul Chai , Soo-Guy Rho
发明人： Nam-Seok Roh , Mun-Pyo Hong , Chong-Chul Chai , Soo-Guy Rho
IPC分类号： G02F1/13357 , G02F1/133 , G02F1/1335 , G02F1/1343 , G02F1/1345 , G02F1/1368
CPC分类号： G02F1/133514 , G02F2201/52 , G09G3/3614
摘要： Pixels of red, blue and green are sequentially arranged in the row. The red and green pixels are alternately arranged in the column while the blue pixels being repeatedly arranged in the column. The four red and green pixels surrounding the two blue pixels at the two neighboring pixel rows face each other around the blue pixels. Gate lines are arranged at the respective rows to transmit scanning signals. Data lines cross over the gate lines in an insulating manner, and are arranged at the respective columns to transmit picture signals. Pixel electrodes and thin film transistor are formed at respective pixels. The blue pixel has the same area as or an area smaller than the red and green pixels. The pixel electrodes are overlapped with the gate or the data lines via a passivation layer of low dielectric organic material or an insulating material such as SiOC, SiOF.
摘要翻译：红色，蓝色和绿色的像素依次排列在行中。红色和绿色像素交替排列在列中，而蓝色像素被重复排列在列中。围绕两个相邻像素行的两个蓝色像素的四个红色和绿色像素围绕蓝色像素彼此面对。栅极线被布置在相应的行以发射扫描信号。数据线以绝缘方式跨越栅极线，并且布置在各列处以传输图像信号。像素电极和薄膜晶体管形成在各个像素处。蓝色像素具有与红色和绿色像素相同的面积或更小的面积。像素电极经由低介电有机材料的钝化层或绝缘材料如SiOC，SiOF与栅极或数据线重叠。

65. 发明授权

US06445004B1 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
标题翻译：配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法
公开(公告)号：US06445004B1
公开(公告)日：2002-09-03
申请号：US09617311
申请日：2000-07-14
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
IPC分类号： H01L2904
CPC分类号： G02F1/136286 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.
摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或半导体显示器以及Al层或Cr层。由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

66. 发明授权

US08749476B2 Electrophoretic display device 有权
标题翻译：电泳显示装置
公开(公告)号：US08749476B2
公开(公告)日：2014-06-10
申请号：US11140850
申请日：2005-05-31
申请人： Nam-Seok Roh , Mun-Pyo Hong
发明人： Nam-Seok Roh , Mun-Pyo Hong
IPC分类号： G09G3/34 , G06F3/042
CPC分类号： G02F1/167 , G09G3/344 , G09G2300/0809 , G09G2360/14
摘要： A electrophoretic display device is provided, which includes: a thin film transistor array panel including a substrate, gate and data lines formed on the substrate and crossing each other, switching thin film transistors electrically connected to the gate and data lines, a photo sensor formed on the substrate, and pixel electrodes electrically connected to the switching thin film transistors; a common electrode panel facing the thin film transistor array panel and having a common electrode; and a display layer disposed between the thin film transistor array panel and the common electrode panel. The display layer includes micro capsules containing negative and positive pigment particles.
摘要翻译：提供了一种电泳显示装置，其包括：薄膜晶体管阵列面板，包括形成在基板上并彼此交叉的基板，栅极和数据线，开关电连接到栅极和数据线的薄膜晶体管，形成的光电传感器和与开关薄膜晶体管电连接的像素电极; 面对薄膜晶体管阵列面板并具有公共电极的公共电极面板; 以及设置在薄膜晶体管阵列面板和公共电极面板之间的显示层。显示层包括含有负性和正性颜料颗粒的微胶囊。

67. 发明授权

US08107586B2 Shift register and display device including the same 有权
标题翻译：移位寄存器和显示设备包括相同
公开(公告)号：US08107586B2
公开(公告)日：2012-01-31
申请号：US11078985
申请日：2005-03-11
申请人： Kyong-Ju Shin , Chong-Chul Chae , Mun-Pyo Hong , Cheol-Woo Park , Nam-Seok Roh
发明人： Kyong-Ju Shin , Chong-Chul Chae , Mun-Pyo Hong , Cheol-Woo Park , Nam-Seok Roh
IPC分类号： G11C19/00
CPC分类号： G09G3/3677 , G09G2310/0281 , G09G2310/0286 , G09G2320/0223 , G09G2320/041 , G09G2330/021 , G11C19/28
摘要： A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage includes a set terminal, a reset terminal, a clock terminal, and first and second output terminals.
摘要翻译：移位寄存器包括彼此连接的级，其中每一级根据时钟信号中的任何一个和两个不同级中的每一个的输出产生输出信号。每个时钟信号具有小于50％的占空比和与每个其它时钟信号不同的相位。显示装置包括像素，信号线，以及第一和第二移位寄存器，每个移位寄存器各自具有彼此连接的级并且向信号线产生输出信号。每个级包括设置终端，复位终端，时钟终端以及第一和第二输出端。

68. 发明授权

US07507996B2 Contact structure of a wiring and a thin film transistor array panel including the same 失效
标题翻译：布线的接触结构和包括该布线的薄膜晶体管阵列面板
公开(公告)号：US07507996B2
公开(公告)日：2009-03-24
申请号：US10754572
申请日：2004-01-12
申请人： Mun-Pyo Hong , Sang-Gab Kim
发明人： Mun-Pyo Hong , Sang-Gab Kim
IPC分类号： H01L27/12
CPC分类号： G02F1/1362 , G02F1/136286 , H01L27/124 , H01L27/1288 , H01L29/458
摘要： First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers.
摘要翻译：首先，将由铝基材料制成的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。形成栅绝缘层，依次形成半导体层和欧姆接触层。接下来，沉积包括下层Cr的导体层和铝基材料的上层，并构图以形成包括与栅极线相交的数据线，源电极，漏电极和数据焊盘的数据线。然后，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，沉积非晶硅层，执行退火处理，以在漏电极，栅极pa和数据焊盘上形成通过接触孔露出的层间反应层。然后，去除非晶硅层。接下来，IZO被沉积和图案化以分别形成像素电极，冗余栅极焊盘和冗余数据焊盘，并经由层间反应层电连接到漏电极，栅极焊盘和数据焊盘。

69. 发明授权

US07507994B2 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07507994B2
公开(公告)日：2009-03-24
申请号：US11625694
申请日：2007-01-22
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Doug-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Doug-Gyu Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

70. 发明授权

US07507594B2 Contact portion and manufacturing method thereof, thin film transistor array panel and manufacturing method thereof 有权
标题翻译：接触部分及其制造方法，薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07507594B2
公开(公告)日：2009-03-24
申请号：US10554718
申请日：2005-02-11
申请人： Jong-Hyun Seo , Mun-Pyo Hong , Dae-Ok Kim
发明人： Jong-Hyun Seo , Mun-Pyo Hong , Dae-Ok Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a contact portion is provided, which includes: forming a first signal line on a substrate (110), forming a insulating layer (140) covering the first signal line and having a contact hole (182, 185) exposing the first signal line; forming a contact layer (700) on the exposed surface of the first signal through the contact hole; and forming a second signal line (82, 190) connected to the first signal line via the contact layer. Wherein the first signal line is made of Al or Al alloy, and the second signal line is made of ITO or IZO.
摘要翻译：提供一种制造接触部分的方法，其包括：在衬底（110）上形成第一信号线，形成覆盖第一信号线的绝缘层（140），并具有暴露第一信号线的接触孔（182,185）信号线通过接触孔在第一信号的暴露表面上形成接触层（700）; 以及形成经由所述接触层连接到所述第一信号线的第二信号线（82,190）。其中第一信号线由Al或Al合金制成，第二信号线由ITO或IZO制成。

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