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61. 发明授权

US06458677B1 Process for fabricating an ONO structure 有权
标题翻译：制造ONO结构的方法
公开(公告)号：US06458677B1
公开(公告)日：2002-10-01
申请号：US09433186
申请日：1999-10-25
申请人： Dawn M. Hopper , David K. Foote , Bharath Rangarajan
发明人： Dawn M. Hopper , David K. Foote , Bharath Rangarajan
IPC分类号： H01L213205
CPC分类号： H01L21/28282 , H01L21/3144 , H01L29/7923 , Y10S438/954
摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the sequential formation of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer using an in-situ deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. To avoid exposure to ambient atmosphere, the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer are sequentially formed using either a PECVD or a SACVD process.
摘要翻译：在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用原位沉积工艺顺序形成第一氧化硅层，氮化硅层和第二氧化硅层，其中氮化硅层在形成顶部氧化物层之前不暴露于环境大气中。为了避免暴露于环境大气中，使用PECVD或SACVD工艺顺序地形成第一氧化硅层，氮化硅层和第二氧化硅层。

62. 发明授权

US06444373B1 Modification of mask layout data to improve mask fidelity 有权
标题翻译：修改掩模布局数据以提高掩码保真度
公开(公告)号：US06444373B1
公开(公告)日：2002-09-03
申请号：US09596954
申请日：2000-06-16
申请人： Ramkumar Subramanian , Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Ramkumar Subramanian , Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： G03F900
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70441
摘要： The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.
摘要翻译：本发明涉及一种修改掩模布局数据以提高掩模制造的保真度的系统和方法。该系统和方法包括确定掩模布局设计和掩模特征之间的写入差异，并产生尺寸校正。尺寸校正可用于修改掩模布局数据和/或存储在数据库中。

63. 发明授权

US06441418B1 Spacer narrowed, dual width contact for charge gain reduction 有权
标题翻译：间距变窄，双宽度接触，减少电荷
公开(公告)号：US06441418B1
公开(公告)日：2002-08-27
申请号：US09430848
申请日：1999-11-01
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L31062
CPC分类号： H01L21/76829 , H01L21/76802 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, forming spacers along the side walls of the first aperture, creating a second aperture in the first insulating layer below the first aperture, and filling the aperture with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.
摘要翻译：本文公开了在集成电路中形成接触的方法。该方法包括在包括第一和第二栅极结构的半导体衬底之上提供第一绝缘层，在第一绝缘层上提供蚀刻停止层，在蚀刻停止层上方提供第二绝缘层，在第二绝缘层中形成第一孔在第一和第二栅极结构之间，沿着第一孔的侧壁形成间隔物，在第一孔下方的第一绝缘层中形成第二孔，并用导电材料填充孔以形成接触。第一孔具有第一孔径宽度并延伸到蚀刻停止层。第二孔径具有小于第一孔径宽度的第二孔径宽度。

64. 发明授权

US06423479B1 Cleaning carbon contamination on mask using gaseous phase 失效
标题翻译：使用气相清洁面罩上的碳污染
公开(公告)号：US06423479B1
公开(公告)日：2002-07-23
申请号：US09495165
申请日：2000-01-31
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
IPC分类号： G03F726
CPC分类号： G03F1/82
摘要： In one embodiment, the present invention relates to a method of processing a lithography mask, involving the steps of exposing a lithography substrate with actinic radiation through the lithography mask in a chamber; removing the lithography mask from the chamber, wherein the lithography mask contains carbon contaminants; and contacting the lithography mask with sulfur trioxide thereby reducing the carbon contaminants thereon.
摘要翻译：在一个实施例中，本发明涉及一种处理光刻掩模的方法，包括以下步骤：将具有光化辐射的光刻基底通过室中的光刻掩模曝光; 从所述腔室去除所述光刻掩模，其中所述光刻掩模含有碳污染物; 并使光刻掩模与三氧化硫接触，从而减少其上的碳污染物。

65. 发明授权

US06416933B1 Method to produce small space pattern using plasma polymerization layer 失效
标题翻译：使用等离子体聚合层产生小空间图案的方法
公开(公告)号：US06416933B1
公开(公告)日：2002-07-09
申请号：US09283889
申请日：1999-04-01
申请人： Bhanwar Singh , Bharath Rangarajan , Wenge Yang
发明人： Bhanwar Singh , Bharath Rangarajan , Wenge Yang
IPC分类号： G03C500
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/0337 , H01L21/0338 , H01L21/31138 , H01L21/31144 , H01L21/312
摘要： The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. A polymer layer is formed to be conformal to the patterned photoresist layer and exposed portions of the underlayer. The polymer layer is etched to form polymer sidewalls, the polymer sidewalls reducing the smallest space dimension of the exposed underlayer area to d2, wherein d2
摘要翻译：本发明涉及一种形成蚀刻掩模的方法。图案化光致抗蚀剂层，其中d1是光致抗蚀剂层下面的层的暴露区域的最小空间尺寸。聚合物层被形成为与图案化的光致抗蚀剂层和底层的暴露部分共形。蚀刻聚合物层以形成聚合物侧壁，聚合物侧壁将暴露的底层区域的最小空间尺寸减小到d2，其中d2

66. 发明授权

US06376013B1 Multiple nozzles for dispensing resist 有权
标题翻译：用于分配抗蚀剂的多个喷嘴
公开(公告)号：US06376013B1
公开(公告)日：2002-04-23
申请号：US09413143
申请日：1999-10-06
申请人： Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Michael K. Templeton
发明人： Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Michael K. Templeton
IPC分类号： B05D100
CPC分类号： H01L21/6715 , B05B7/0408 , B05C11/02 , B05C11/08 , G03F7/162
摘要： A system and method is provided that facilitates the application of a uniform layer of photoresist material spincoated onto a semiconductor substrate (e.g wafer). The present invention accomplishes this end by utilizing a measurement system that measures the thickness uniformity of the photoresist material applied on a test wafer by a nozzle, and then adjusting the viscosity of the photoresist material by varying the ratio in a solvent/resist mixture, and/or adjusting the temperature of the mixture. A system and method that employs a plurality of nozzles is also provided that disperses resist at different annular regions on a wafer to facilitate the application of a uniform layer of photoresist material spincoated onto the wafer. The system and method utilize a measurement system that measures the thickness and thickness uniformity of each layer of photoresist material applied at each annular region of the wafer. The measured thickness uniformity and overall thickness for each annular region is then used to adjust the volume and viscosity of a solvent/resist mixture applied through each nozzle.
摘要翻译：提供了一种系统和方法，其有利于将均匀的光致抗蚀剂材料层涂覆在半导体衬底（例如晶片）上。本发明通过利用测量系统来实现这一目的，测量系统通过喷嘴测量施加在测试晶片上的光致抗蚀剂材料的厚度均匀性，然后通过改变溶剂/抗蚀剂混合物中的比例来调节光致抗蚀剂材料的粘度，以及 /或调整混合物的温度。还提供了使用多个喷嘴的系统和方法，其将抗蚀剂分散在晶片上的不同环形区域，以便于将均匀的光致抗蚀剂材料层涂覆在晶片上。该系统和方法利用测量系统，其测量在晶片的每个环形区域施加的每层光致抗蚀剂材料的厚度和厚度均匀性。然后使用测量的每个环形区域的厚度均匀性和总厚度来调节通过每个喷嘴施加的溶剂/抗蚀剂混合物的体积和粘度。

67. 发明授权

US06371134B1 Ozone cleaning of wafers 有权
公开(公告)号：US06371134B1
公开(公告)日：2002-04-16
申请号：US09495014
申请日：2000-01-31
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
IPC分类号： B08B700
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.

68. 发明授权

US06277544B1 Reverse lithographic process for semiconductor spaces 有权
标题翻译：半导体空间反向光刻工艺
公开(公告)号：US06277544B1
公开(公告)日：2001-08-21
申请号：US09329153
申请日：1999-06-09
申请人： Bhanwar Singh , Bharath Rangarajan , Ursula Q. Quinto
发明人： Bhanwar Singh , Bharath Rangarajan , Ursula Q. Quinto
IPC分类号： G03C500
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/76838
摘要： A reverse lithographic process is provided for more densely packing semiconductors onto a semiconductor wafer. A semiconductor wafer having deposited a number of layers of semiconductor materials has a photoresist deposited which is patterned with the spaces as lines, and then developed and trimmed. A polymer is deposited over the space photoresist structures and, when hardened, is subject to planarizing to expose the photoresist. The photoresist is removed leaving a reverse image polymer which is then used as a mask to anisotropically etch the spaces to form the closely spaced devices.
摘要翻译：提供反向光刻工艺用于在半导体晶片上更密集地堆叠半导体。已经沉积了多层半导体材料的半导体晶片具有沉积的光致抗蚀剂，其以空间为线图案化，然后显影和修整。聚合物沉积在空间光致抗蚀剂结构上，并且当硬化时，进行平面化以暴露光致抗蚀剂。去除光致抗蚀剂留下反向图像聚合物，然后将其用作掩模以各向异性地蚀刻空间以形成紧密间隔的装置。

69. 发明授权

US06274289B1 Chemical resist thickness reduction process 有权
标题翻译：化学抗蚀剂厚度降低过程
公开(公告)号：US06274289B1
公开(公告)日：2001-08-14
申请号：US09708104
申请日：2000-11-06
申请人： Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Ursula Q. Quinto
发明人： Ramkumar Subramanian , Michael K. Templeton , Bharath Rangarajan , Ursula Q. Quinto
IPC分类号： G03F711
CPC分类号： G03F7/168 , G03F7/40
摘要： In one embodiment, the present invention relates to a method of treating a resist layer involving the steps of providing the resist layer having a first thickness, the resist layer comprising a polymer having a labile group; contacting a coating containing at least one cleaving compound with the resist layer to form a deprotected resist layer at an interface between the resist layer and the coating; and removing the coating and the deprotected resist layer leaving a resist having a second thickness, wherein the second thickness is smaller than the first thickness.
摘要翻译：在一个实施方案中，本发明涉及一种处理抗蚀剂层的方法，包括以下步骤：提供具有第一厚度的抗蚀剂层，抗蚀剂层包含具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与抗蚀剂层接触，以在抗蚀剂层和涂层之间的界面处形成去保护的抗蚀剂层; 以及去除涂层和去保护的抗蚀剂层，留下具有第二厚度的抗蚀剂，其中第二厚度小于第一厚度。

70. 发明授权

US06248635B1 Process for fabricating a bit-line in a monos device using a dual layer hard mask 有权
标题翻译：使用双层硬掩模在单体器件中制造位线的工艺
公开(公告)号：US06248635B1
公开(公告)日：2001-06-19
申请号：US09426205
申请日：1999-10-25
申请人： David K. Foote , Hideki Komori , Bharath Rangarajan , Steven K. Park
发明人： David K. Foote , Hideki Komori , Bharath Rangarajan , Steven K. Park
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , Y10S438/954
摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure to overlie the semiconductor substrate. Thereafter, a thin mask layer is formed to overlie the ONO structure to protect the ONO structure during a selective etch of a thick mask layer. The thick mask layer is formed to overlie the thin mask layer to protect the ONO structure during boron and arsenic implants. Thereafter, an etch process is performed in the ONO structure and a silicon oxide layer is formed to fill the etched area. A chemical-mechanical-polishing process is performed to planarize the silicon oxide layer and to form a planar surface continuous with an upper surface of the thick mask layer. The planarized silicon oxide layer functions as a bit-line oxide layer.
摘要翻译：用于制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成ONO结构以覆盖半导体衬底。此后，形成薄的掩模层以覆盖ONO结构以在厚掩模层的选择性蚀刻期间保护ONO结构。形成厚掩模层以覆盖薄掩模层以在硼和砷注入中保护ONO结构。此后，在ONO结构中进行蚀刻处理，并且形成氧化硅层以填充蚀刻区域。进行化学机械抛光工艺以平坦化氧化硅层并形成与厚掩模层的上表面连续的平面。平坦化的氧化硅层用作位线氧化物层。

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