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    • 62. 发明授权
    • System and method for active control of etch process
    • 用于主动控制蚀刻工艺的系统和方法
    • US07052575B1
    • 2006-05-30
    • US09845454
    • 2001-04-30
    • Bharath RangarajanBhanwar SinghRamkumar Subramanian
    • Bharath RangarajanBhanwar SinghRamkumar Subramanian
    • C23F1/00
    • H01L21/67253H01J37/32935H01L21/67063H01L22/34
    • A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.
    • 提供了一种用于调节蚀刻工艺的系统。 该系统包括一个或多个光源,每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集,该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供蚀刻相关数据,该处理器确定晶片的相应部分的蚀刻的可接受性。 该系统还包括一个或多个蚀刻装置,每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。
    • 64. 发明授权
    • Using scatterometry to obtain measurements of in circuit structures
    • 使用散射法获得电路结构的测量
    • US06912438B2
    • 2005-06-28
    • US10277016
    • 2002-10-21
    • Bryan K. ChooBhanwar SinghRamkumar SubramanianBharath Rangarajan
    • Bryan K. ChooBhanwar SinghRamkumar SubramanianBharath Rangarajan
    • G01N21/47H01L21/66G06F19/00
    • H01L22/20G01N21/4738H01L2924/0002H01L2924/00
    • A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.
    • 公开了用于监测和控制半导体制造工艺的系统和方法。 根据基于散射法的技术进行测量,该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。 可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。 另外,例如,可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。 在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产,因为测试光栅结构可能不需要在晶片内形成,并且还有助于对实际影响芯片性能的元件的控制。
    • 65. 发明授权
    • Fab correlation system
    • Fab相关系统
    • US06878560B1
    • 2005-04-12
    • US10302091
    • 2002-11-22
    • Bharath RangarajanBhanwar SinghRamkumar Subramanian
    • Bharath RangarajanBhanwar SinghRamkumar Subramanian
    • H01L21/66
    • H01L22/20G05B2219/31457G05B2219/32191G05B2219/45031H01L2924/0002H01L2924/00
    • A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
    • 由多个工厂组成的系统,其可操作地耦合并且共享来自公共框架的数据以用于生产。 该晶圆厂可以通过互联网,蜂窝,光学,固定电话,微波和卫星通信装置等耦合。 可以将数据传送到中央集成的相关实体或从多个分散的相关实体传送到和/或从中央集成的相关实体接收数据。 制造厂发送和接收与生产信息相关的相关数据,例如公差,关键尺寸,几何形状等。 相关实体具有通过对接收到的相关数据执行概率计算并利用所得到的信息来维持远程位置处的相关参数来增加产量的能力。 执行的计算可以包括诸如贝叶斯推理等的计算。 该系统固有地排除了在不同晶圆厂或模具位置之间物理传输参数测试实体的必要性。
    • 67. 发明授权
    • Use of scatterometry/reflectometry to measure thin film delamination during CMP
    • 在CMP期间使用散射/反射测量薄膜分层
    • US06702648B1
    • 2004-03-09
    • US10277559
    • 2002-10-22
    • Steven C. AvanzinoBhanwar SinghBharath RangarajanRamkumar Subramanian
    • Steven C. AvanzinoBhanwar SinghBharath RangarajanRamkumar Subramanian
    • B24B4900
    • B24B37/013B24B49/12
    • One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.
    • 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统,使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器,其中每个传感器的至少一部分被集成到抛光系统中,以便向计量系统提供数据,并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分,并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。
    • 69. 发明授权
    • Monitor CMP process using scatterometry
    • 使用散点法监测CMP过程
    • US06594024B1
    • 2003-07-15
    • US09886863
    • 2001-06-21
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBharath RangarajanCarmen Morales
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBharath RangarajanCarmen Morales
    • G01B1128
    • B24B37/005B24B49/12G01N21/47G01N21/9501H01L21/30625
    • One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.
    • 本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统,以便确定包括晶片的CMP工艺端点,其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库,以确定晶片的状态。 另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法,其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。
    • 70. 发明授权
    • Measure fluorescence from chemical released during trim etch
    • 测量在修剪蚀刻期间释放的化学物质的荧光
    • US06448097B1
    • 2002-09-10
    • US09911236
    • 2001-07-23
    • Bhanwar SinghBharath RangarajanRamkumar Subramanian
    • Bhanwar SinghBharath RangarajanRamkumar Subramanian
    • H01L3126
    • G01N21/64G01N2021/6417H01L22/26
    • A system and method is provided for determining and controlling development of a semiconductor substrate employing fluorescence spectroscopy. One aspect of the invention relates to a system and method employing fluorescence spectroscopy to facilitate control of a chemical trim etch process during development of a photoresist material layer. The chemical trim etch process comprises applying a trim compound or material to a patterned photoresist. The trim compound or material is diffusable into the sides and top of the patterned resist. The diffused regions of the resist are soluble in a developer, which facilitates creating smaller features in the patterned photoresist. The fluorescence spectroscopy system can be employed to measure isolated and dense gratings or CDs and use the evolution of the CD to determine when to terminate the chemical trim process.
    • 提供了一种使用荧光光谱法确定和控制半导体衬底的开发的系统和方法。 本发明的一个方面涉及使用荧光光谱学来促进在光致抗蚀剂材料层的显影期间控制化学修剪蚀刻工艺的系统和方法。 化学修剪蚀刻工艺包括将修剪化合物或材料施加到图案化的光致抗蚀剂上。 修整组合物或材料可扩散到图案化抗蚀剂的侧面和顶部。 抗蚀剂的扩散区域可溶于显影剂,这有助于在图案化的光致抗蚀剂中产生更小的特征。 荧光光谱系统可用于测量孤立和致密的光栅或CD,并使用CD的演变来确定何时终止化学修饰过程。