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61. 发明申请

US20100174966A1 DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION 有权
标题翻译：提供1位错误校正的设备和方法
公开(公告)号：US20100174966A1
公开(公告)日：2010-07-08
申请号：US12651586
申请日：2010-01-04
申请人： Yong June KIM , Jae Hong KIM , Jun Jin KONG
发明人： Yong June KIM , Jae Hong KIM , Jun Jin KONG
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , H03M13/1105 , H03M13/1108
摘要： A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.
摘要翻译：提供1位纠错方法。在该方法中，基于在连接到每个可变节点的校验节点中不满足奇偶校验条件的不满足校验节点的数量和对应于检测变量的位的错误来检测发生错误的变量节点节点被更正。

62. 发明申请

US20100115225A1 Memory Device and Memory System Including the Same 审中-公开
标题翻译：内存设备和包含其的内存系统
公开(公告)号：US20100115225A1
公开(公告)日：2010-05-06
申请号：US12577842
申请日：2009-10-13
申请人： Jaehong Kim , Heeseok Eun , Yong June Kim , Seung-Hwan Song
发明人： Jaehong Kim , Heeseok Eun , Yong June Kim , Seung-Hwan Song
IPC分类号： G06F12/00
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0679 , G11C11/5621 , G11C16/349
摘要： Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed.
摘要翻译：提供了一种存储器件。存储器件包括字线和连接到字线的多个存储器单元。多个存储单元形成页面，并且可以改变构成页面的扇区数量和每个扇区的大小。

63. 发明申请

US20090307566A1 ITERATIVE DECODING METHOD AND APPARATUS 有权
标题翻译：迭代解码方法和装置
公开(公告)号：US20090307566A1
公开(公告)日：2009-12-10
申请号：US12475640
申请日：2009-06-01
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
摘要翻译：公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在执行迭代次数期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

64. 发明申请

US20090287975A1 Memory device and method of managing memory data error 有权
标题翻译：内存设备和管理内存数据错误的方法
公开(公告)号：US20090287975A1
公开(公告)日：2009-11-19
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/10 , G11C16/04 , G11C16/06 , G11C16/02 , H03M13/03
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

65. 发明申请

US20090276687A1 METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA 有权
标题翻译：编码和解码多级数据的方法
公开(公告)号：US20090276687A1
公开(公告)日：2009-11-05
申请号：US12429718
申请日：2009-04-24
申请人： Yong June KIM , Jae Hong KIM , Kyoung Lae CHO , Jun Jin KONG , Ki Jun LEE , Ha Bong CHUNG , Keun Sung CHOI
发明人： Yong June KIM , Jae Hong KIM , Kyoung Lae CHO , Jun Jin KONG , Ki Jun LEE , Ha Bong CHUNG , Keun Sung CHOI
IPC分类号： H03M13/19 , G06F11/10 , H03M13/45
CPC分类号： H03M13/451 , G06F11/1072
摘要： A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.
摘要翻译：一种编码多位电平数据的方法包括：根据传输符号确定产生的误差模式的范围，根据误差模式的范围来编码与发送符号对应的P位电平的M位电平，并且排除P位电平的PM位电平的编码。变量P是至少为2的值的自然数，变量M是小于P的自然数。

66. 发明授权

US08806302B2 Semiconductor memory device and data processing method thereof 有权
标题翻译：半导体存储器件及其数据处理方法
公开(公告)号：US08806302B2
公开(公告)日：2014-08-12
申请号：US12654578
申请日：2009-12-23
申请人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
发明人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
IPC分类号： G11C29/00
CPC分类号： G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.
摘要翻译：提供了一种半导体存储器件中的数据处理方法。数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

67. 发明授权

US08782490B2 Data storage device and program method that modifies arrangement of program data to eliminate interfering data patterns 有权
标题翻译：数据存储装置和程序方法，其修改程序数据的排列以消除干扰数据模式
公开(公告)号：US08782490B2
公开(公告)日：2014-07-15
申请号：US13103460
申请日：2011-05-09
申请人： Yong June Kim , Kyoung Lae Cho , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Hong Rak Son
IPC分类号： G11C29/00 , G06F11/10 , G11C29/10 , G11C29/04 , H03M7/46
CPC分类号： G06F11/1048 , G11C29/10 , G11C2029/0411 , H03M7/46
摘要： A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.
摘要翻译：数据存储装置包括包括多个存储器单元和存储器控制器的非易失性存储器件。存储器控制器被配置为修改程序数据的布置并且将修改的程序数据编程到多个存储器单元中。存储器控制器修改程序数据以消除给定的数据模式，从修改的程序数据导致相邻存储器单元之间的物理干扰。

68. 发明授权

US08607118B2 Iterative decoding method and apparatus 有权
标题翻译：迭代解码方法和装置
公开(公告)号：US08607118B2
公开(公告)日：2013-12-10
申请号：US12475640
申请日：2009-06-01
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
摘要翻译：公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在迭代次数的执行期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

69. 发明授权

US08482977B2 Multi-bit cell memory devices using error correction coding and methods of operating the same 有权
标题翻译：使用纠错编码的多位单元存储器件及其操作方法
公开(公告)号：US08482977B2
公开(公告)日：2013-07-09
申请号：US13039004
申请日：2011-03-02
申请人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
发明人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04
摘要： A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.
摘要翻译：存储器件包括多个多位存储器单元。根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。码字的比特组可以是连续比特的组。在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

70. 发明授权

US08397116B2 Decoding method and memory system device using the same 有权
标题翻译：解码方法和使用其的内存系统设备
公开(公告)号：US08397116B2
公开(公告)日：2013-03-12
申请号：US12652768
申请日：2010-01-06
申请人： Jong-seon No , Beom-kyu Shin , Ho-sung Park , Yong-june Kim , Jae-hong Kim , Young-hwan Lee , Jun-jin Kong
发明人： Jong-seon No , Beom-kyu Shin , Ho-sung Park , Yong-june Kim , Jae-hong Kim , Young-hwan Lee , Jun-jin Kong
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1108 , H03M13/3707 , H03M13/451 , H03M13/458 , H04L1/0045 , H04L1/0057
摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.
摘要翻译：解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

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