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61. 发明授权

US07279267B2 Method for manipulating the topography of a film surface 有权
标题翻译：操纵膜表面形貌的方法
公开(公告)号：US07279267B2
公开(公告)日：2007-10-09
申请号：US10644356
申请日：2003-08-19
申请人： Tsai-Sheng Gau , Burn Jeng Lin
发明人： Tsai-Sheng Gau , Burn Jeng Lin
IPC分类号： G03F7/26
CPC分类号： G03F7/40 , G03F1/50 , G03F7/0035 , G03F7/2026
摘要： A method for selectively altering a thickness of a radiation sensitive polymer layer including providing a substrate including at least one radiation sensitive polymer layer having a first thickness topography; exposing the at least one radiation sensitive polymer layer through a mask having a predetermined radiant energy transmittance distribution to selectively expose predetermined areas of the at least one sensitive polymer layer to predetermined radiant energy dosages; and, developing the at least one radiation sensitive polymer layer to alter the first thickness topography of the at least one radiation sensitive polymer layer to produce a second thickness topography.
摘要翻译：一种用于选择性地改变辐射敏感聚合物层的厚度的方法，包括提供包括具有第一厚度形貌的至少一个辐射敏感聚合物层的基底; 使所述至少一个辐射敏感聚合物层通过具有预定辐射能透射率分布的掩模曝光，以选择性地将所述至少一个敏感聚合物层的预定区域暴露于预定的辐射能量剂量; 以及显影所述至少一个辐射敏感聚合物层以改变所述至少一个辐射敏感聚合物层的第一厚度形貌以产生第二厚度拓扑。

62. 发明申请

US20070092840A1 System and method for photolithography in semiconductor manufacturing 有权
标题翻译：半导体制造中的光刻系统和方法
公开(公告)号：US20070092840A1
公开(公告)日：2007-04-26
申请号：US11259589
申请日：2005-10-26
申请人： Kuei Chen , Chin-Hsiang Lin , Tsai-Sheng Gau , Chun-Kuang Chen , Hsiao-Tzu Lu , Fu-Jye Liang
发明人： Kuei Chen , Chin-Hsiang Lin , Tsai-Sheng Gau , Chun-Kuang Chen , Hsiao-Tzu Lu , Fu-Jye Liang
IPC分类号： G03F7/20
CPC分类号： G03F7/70333 , G03F7/70091 , G03F7/70108 , G03F7/70283 , G03F7/70641 , G03F9/7026
摘要： A method for photolithography in semiconductor manufacturing includes providing a substrate for a wafer and providing a mask for exposing the wafer. The wafer is exposed by utilizing a combination of high angle illumination and focus drift exposure methods.
摘要翻译：半导体制造中的光刻方法包括提供用于晶片的衬底并提供用于暴露晶片的掩模。通过利用高角度照明和聚焦漂移曝光方法的组合来曝光晶片。

63. 发明授权

US07180572B2 Immersion optical projection system 有权
标题翻译：浸入式光学投影系统
公开(公告)号：US07180572B2
公开(公告)日：2007-02-20
申请号：US11009505
申请日：2004-12-10
申请人： Jen-Chieh Shih , Burn-Jeng Lin , Tsai-Sheng Gau , Ru-Gun Liu , Chun-Kuang Chen , Chin-Hsiang Lin , Horng-Huei Tseng
发明人： Jen-Chieh Shih , Burn-Jeng Lin , Tsai-Sheng Gau , Ru-Gun Liu , Chun-Kuang Chen , Chin-Hsiang Lin , Horng-Huei Tseng
IPC分类号： G03B27/42
CPC分类号： G03F7/70341
摘要： An immersion optical projection system for photolithography is provided. A transparent plate is located between a last lens element and the wafer during a usage of the system. The transparent plate has a lens-side surface and a wafer-side surface. The system is adapted to have a layer of lens-side fluid located between the last lens element and the lens-side surface of the transparent plate, e.g., when the last lens element is operably located over the wafer during a photolithography process. The system is also adapted to have a layer of wafer-side fluid located between the wafer-side surface of the transparent plate and the wafer, during a usage of the system. The wafer-side fluid may or may not be fluidly connected to the lens-side fluid. The wafer-side fluid may or may not differ from the lens-side fluid.
摘要翻译：提供了一种用于光刻的浸没式光学投影系统。在使用系统期间，透明板位于最后一个透镜元件和晶片之间。透明板具有透镜侧表面和晶片侧表面。该系统适于具有位于最后透镜元件和透明板的透镜侧表面之间的透镜侧流体层，例如当光刻工艺期间最后一个透镜元件可操作地位于晶片上方时。该系统还适于在系统的使用期间具有位于透明板的晶片侧表面和晶片之间的晶片侧流体层。晶片侧流体可以或可以不流体地连接到透镜侧流体。晶片侧流体可以或可以不与透镜侧流体不同。

64. 发明申请

US20050286033A1 Immersion lithography system with wafer sealing mechanisms 有权
标题翻译：具有晶片密封机构的浸没光刻系统
公开(公告)号：US20050286033A1
公开(公告)日：2005-12-29
申请号：US10874982
申请日：2004-06-23
申请人： Burn Lin , Tsai-Sheng Gau , Chun-Kung Chen , Ru-Gun Liu , Shing Yu , Jen Shih
发明人： Burn Lin , Tsai-Sheng Gau , Chun-Kung Chen , Ru-Gun Liu , Shing Yu , Jen Shih
IPC分类号： G03B27/42 , G03F7/20
CPC分类号： G03F7/70808 , G03F7/70341
摘要： An immersion lithography system is disclosed to comprise a fluid containing feature for providing an immersion fluid for performing immersion lithography on a wafer, and a seal ring covering a predetermined portion of a wafer edge for preventing the immersion fluid from leaking through the covered portion of the wafer edge while the fluid is used for the immersion lithography.
摘要翻译：公开了一种浸没式光刻系统，其包括用于提供用于在晶片上进行浸没式光刻的浸没流体的流体容纳特征，以及覆盖晶片边缘的预定部分的密封环，用于防止浸没流体泄漏通过晶片边缘，同时流体用于浸没光刻。

65. 发明授权

US08837810B2 System and method for alignment in semiconductor device fabrication 有权
标题翻译：用于在半导体器件制造中对准的系统和方法
公开(公告)号：US08837810B2
公开(公告)日：2014-09-16
申请号：US13431668
申请日：2012-03-27
申请人： Yen-Liang Chen , Te-Chih Huang , Chen-Ming Wang , Chih-Ming Ke , Tsai-Sheng Gau
发明人： Yen-Liang Chen , Te-Chih Huang , Chen-Ming Wang , Chih-Ming Ke , Tsai-Sheng Gau
IPC分类号： G06K9/68
CPC分类号： G03F7/70633 , G06T7/001 , G06T7/68 , G06T2207/30148
摘要： A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes.
摘要翻译：确定半导体器件制造中的覆盖误差的方法包括接收形成在衬底上的覆盖标记的图像。所接收的图像被分成第一图像和第二图像，其中第一图像包括形成在基底的第一层上的特征的表示，并且第二图像包括形成在基底的第二层上的特征的表示。确定第一个图像的质量指示符，并确定第二个图像的质量指示符。在一个实施例中，质量指标包括不对称指数。

66. 发明申请

US20130259358A1 SYSTEM AND METHOD FOR ALIGNMENT IN SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：用于在半导体器件制造中对准的系统和方法
公开(公告)号：US20130259358A1
公开(公告)日：2013-10-03
申请号：US13431668
申请日：2012-03-27
申请人： Yen-Liang Chen , Te-Chih Huang , Chen-Ming Wang , Chih-Ming Ke , Tsai-Sheng Gau
发明人： Yen-Liang Chen , Te-Chih Huang , Chen-Ming Wang , Chih-Ming Ke , Tsai-Sheng Gau
IPC分类号： G06K9/68
CPC分类号： G03F7/70633 , G06T7/001 , G06T7/68 , G06T2207/30148
摘要： A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes
摘要翻译：确定半导体器件制造中的覆盖误差的方法包括接收形成在衬底上的覆盖标记的图像。所接收的图像被分成第一图像和第二图像，其中第一图像包括形成在基底的第一层上的特征的表示，并且第二图像包括形成在基底的第二层上的特征的表示。确定第一个图像的质量指示符，并确定第二个图像的质量指示符。在一个实施例中，质量指标包括不对称指数

67. 发明申请

US20120135600A1 METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING 有权
标题翻译：金属相关方法，用于双重方式分割
公开(公告)号：US20120135600A1
公开(公告)日：2012-05-31
申请号：US13006608
申请日：2011-01-14
申请人： Burn Jeng LIN , Tsai-Sheng GAU , Ru-Gun LIU , Wen-Chun Huang
发明人： Burn Jeng LIN , Tsai-Sheng GAU , Ru-Gun LIU , Wen-Chun Huang
IPC分类号： H01L21/44 , G06F17/50
CPC分类号： H01L22/10 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036 , G06F17/5072 , G06F17/5081 , H01L21/31144 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G0-mask-split-rule for space or pitch (or both) between vias, the mask assignment of end vias are given higher priority to ensure good landing of end vias, since they are at higher risk of mislanding. The metal correlated via mask splitting methods enable better via performance, such as lower via resistance, and higher via yield.
摘要翻译：所描述的用于双重图案化技术的通孔掩模分裂方法的实施例使得能够经由图案化以对准下面的金属层或覆盖以减少覆盖误差并增加通过着陆。如果相邻的通孔违反了通孔之间的空间或间距（或两者）的G0-掩模分割规则，则优先考虑末端通孔的掩模分配，以确保最终通孔的良好着陆，因为它们具有较高的误放置风险。通过掩模分离方法相关的金属能够实现更好的通过性能，例如较低的通孔电阻和较高的通孔产量。

68. 发明授权

US08038897B2 Method and system for wafer inspection 有权
标题翻译：晶圆检查方法及系统
公开(公告)号：US08038897B2
公开(公告)日：2011-10-18
申请号：US11671772
申请日：2007-02-06
申请人： Chang-Cheng Hung , Tsai-Sheng Gau
发明人： Chang-Cheng Hung , Tsai-Sheng Gau
IPC分类号： G01R31/00
CPC分类号： G03F1/84 , G06T7/001 , G06T2207/10056 , G06T2207/30148
摘要： A method for inspecting semiconductor wafers patterned by a photomask includes loading a first wafer and scanning a first image of the first wafer, loading a second wafer and scanning a second image of the second wafer, comparing the first and second images, and classifying a difference detected between the first and second images as a potential defect on the photomask. The potential defect includes a haze defect on the photomask.
摘要翻译：用于检查由光掩模图案化的半导体晶片的方法包括加载第一晶片并扫描第一晶片的第一图像，加载第二晶片并扫描第二晶片的第二图像，比较第一和第二图像，以及对差异进行分类在第一和第二图像之间检测作为光掩模上的潜在缺陷。潜在的缺陷包括光掩模上的雾度缺陷。

69. 发明申请

US20110131007A1 Measurement Of Overlay Offset In Semiconductor Processing 有权
标题翻译：半导体处理中覆盖偏移的测量
公开(公告)号：US20110131007A1
公开(公告)日：2011-06-02
申请号：US12957802
申请日：2010-12-01
申请人： Te-Chih Huang , Chih-Ming Ke , Tsai-Sheng Gau
发明人： Te-Chih Huang , Chih-Ming Ke , Tsai-Sheng Gau
IPC分类号： G01B11/14 , G06F15/00
CPC分类号： H01L22/12 , G03F7/70633
摘要： A system for overlay offset measurement in semiconductor manufacturing including a radiation source, a detector, and a calculation unit. The radiation source is operable to irradiate an overlay offset measurement target. The detector is operable to detect a first reflectivity and a second reflectivity of the irradiated overlay offset measurement target. The calculation unit is operable to determine an overlay offset using the detected first and second reflectivity by determining a predetermined overlay offset amount which provides an actual offset of zero.
摘要翻译：一种用于包括辐射源，检测器和计算单元的半导体制造中的覆盖偏移测量的系统。辐射源可操作以照射覆盖偏移测量目标。检测器可操作以检测被照射的覆盖偏移测量目标的第一反射率和第二反射率。计算单元可操作以通过确定提供零的实际偏移量的预定覆盖偏移量来确定使用检测到的第一和第二反射率的覆盖偏移。

70. 发明授权

US07897297B2 Method and system for optimizing intra-field critical dimension uniformity using a sacrificial twin mask 有权
标题翻译：使用牺牲双掩模优化场内临界尺寸均匀性的方法和系统
公开(公告)号：US07897297B2
公开(公告)日：2011-03-01
申请号：US11763269
申请日：2007-06-14
申请人： Chih-Ming Ke , Tsai-Sheng Gau , Shinn-Sheng Yu , Hung-Chang Hsieh
发明人： Chih-Ming Ke , Tsai-Sheng Gau , Shinn-Sheng Yu , Hung-Chang Hsieh
IPC分类号： G03F1/00
CPC分类号： G03F1/44 , G03F1/00
摘要： Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.
摘要翻译：公开了一种用于优化集成电路的场内临界尺寸的方法和系统。提供了集成电路的第一掩模，其包括至少一个器件区域。通过复制第一掩模来提供第二掩模，并且使用第一和第二掩模将光刻操作提供给集成电路，其中使用第二掩模优化集成电路的临界尺寸。第二掩模包括多个牺牲图案，其可以是多个平坦图案或多个光栅图案。

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