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61. 发明授权

US5796293A Voltage boosting circuits having backup voltage boosting capability 失效
标题翻译：具有备用升压能力的升压电路
公开(公告)号：US5796293A
公开(公告)日：1998-08-18
申请号：US748189
申请日：1996-11-12
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： G11C11/413 , G11C5/14 , G11C8/08 , G11C11/407 , H01L21/8242 , H01L27/108 , H02M3/07 , G05F1/10
CPC分类号： G11C5/145 , G11C8/08
摘要： Voltage boosting circuits include backup voltage boosting circuits which are enabled during high current loading conditions when voltage sags in the potential of a boosted signal line(s) are encountered, and which provide independent level detection capability to bypass main voltage level detectors when relatively severe voltage sags are anticipated. In particular, voltage boosting circuits are provided which contain a main voltage boosting circuit and a backup voltage boosting circuit therein. The main voltage boosting circuit is typically powered at a first reference potential (e.g., Vcc) and preferably contains a main level detector, a built-in oscillator and a main pump coupled in series to drive a signal line (e.g., Vpp) to a boosted reference potential which is greater than the first reference potential, if a potential of the signal line drops below a second reference potential. To supplement the voltage boosting capability of the main pump, a backup voltage boosting circuit is provided containing an independent voltage level detector and at least one backup pump coupled in series therewith, to drive the signal line to the boosted reference potential, if the potential of the signal line drops below a third reference potential which may be greater than or equal to the second reference potential. Accordingly, the occurrence of relatively small voltage sags in the potential of the boosted signal line (e.g., Vpp) can trigger the backup pump during anticipated high current loading conditions, while the occurrence of larger voltage sags in the potential can trigger the main pump to assist the backup pump.
摘要翻译：升压电路包括备用升压电路，其在高电流负载状态期间能够在遇到升压信号线的电位的电压骤降时使能，并且当相对严重的电压时提供独立的电平检测能力来旁路主电压电平检测器预计会下滑。特别地，提供了在其中包含主升压电路和备用升压电路的升压电路。主升压电路通常以第一参考电位（例如，Vcc）供电，并且优选地包含主电平检测器，内置振荡器和串联耦合的主泵，以将信号线（例如Vpp）驱动到如果信号线的电位低于第二参考电位，则升高参考电位大于第一参考电位。为了补充主泵的升压能力，提供备用升压电路，其包含独立的电压电平检测器和与串联耦合的至少一个备用泵，以将信号线驱动到升压的参考电位，如果电压信号线下降到可能大于或等于第二参考电位的第三参考电位以下。因此，在预期的高电流负载条件期间，升压信号线的电位（例如，Vpp）中的相对小的电压下降的发生可以触发备用泵，而在电位中较大的电压下降的发生可以触发主泵协助备用泵。

62. 发明授权

US5677886A Sense amplifier circuit in semiconductor memory device 失效
标题翻译：半导体存储器件中的感应放大器电路
公开(公告)号：US5677886A
公开(公告)日：1997-10-14
申请号：US558105
申请日：1995-11-13
申请人： Dong-Il Seo , Sei-Seung Yoon , Se-Jin Jeong
发明人： Dong-Il Seo , Sei-Seung Yoon , Se-Jin Jeong
IPC分类号： G11C11/417 , G11C7/06 , G11C7/12 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C13/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C7/12
摘要： There is provided in the present invention a signal generator which generates a bit line equalization signal and a signal generator which generates a sense amplifier equalization signal to control the bit line equalization circuit and the sense amplifier equalization circuit, respectively. The generated bit line equalization signal and sense amplifier equalization signal both have a voltage level that is at least about equal to, and preferably greater than, an external power supply voltage. The signals generated by these signal generators can thus be used by operating voltages which are much less than was previously possible.
摘要翻译：在本发明中提供了一种产生位线均衡信号的信号发生器和产生读出放大器均衡信号以分别控制位线均衡电路和读出放大器均衡电路的信号发生器。所产生的位线均衡信号和读出放大器均衡信号都具有至少等于并且优选地大于外部电源电压的电压电平。因此，由这些信号发生器产生的信号可以通过比以前可能的操作电压小的操作来使用。

63. 发明授权

US09941196B2 Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device 有权
公开(公告)号：US09941196B2
公开(公告)日：2018-04-10
申请号：US15130904
申请日：2016-04-15
申请人： Ho-Jin Lee , Tae-Je Cho , Dong-Hyeon Jang , Ho-Geon Song , Se-Young Jeong , Un-Byoung Kang , Min-Seung Yoon
发明人： Ho-Jin Lee , Tae-Je Cho , Dong-Hyeon Jang , Ho-Geon Song , Se-Young Jeong , Un-Byoung Kang , Min-Seung Yoon
IPC分类号： H01L21/768 , H01L23/498 , H01L23/48 , H01L25/065 , H01L23/525
CPC分类号： H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

64. 发明授权

US09215604B2 Method and device for updating a database for wireless LAN based positioning 有权
标题翻译：用于更新无线LAN定位的数据库的方法和设备
公开(公告)号：US09215604B2
公开(公告)日：2015-12-15
申请号：US13808328
申请日：2011-06-28
申请人： Suk Yon Kang , Seung Yoon Baek , Hye Min Lee , Chang Seok Lee , Chae Hwan Cho
发明人： Suk Yon Kang , Seung Yoon Baek , Hye Min Lee , Chang Seok Lee , Chae Hwan Cho
IPC分类号： H04L1/00 , H04W24/02 , H04W64/00 , G01S5/02 , H04W84/12
CPC分类号： H04W24/02 , G01S5/021 , G01S5/0252 , H04W64/00 , H04W84/12
摘要： An apparatus for updating a database for wireless LAN based positioning includes a database for storing grid cells divided by pCell ID and base station-derived environment information and wireless LAN environment information matched to the grid cells; a grid cell determining unit for determining an information-unmeasured grid cell among the grid cells, the information-unmeasured grid cell being a grid cell that has unmeasured information among parameters of the wireless LAN environment information matched to the grid cells; an unmeasured parameter checking unit for checking an unmeasured parameter in the information-unmeasured grid cell; a radiowave environment estimating unit for generating radiowave environment estimation information by estimating the unmeasured information based on the unmeasured parameter checked; and a database updating unit for reflecting the radiowave environment estimation information in the information-unmeasured grid cell determined.
摘要翻译：一种用于更新用于基于无线LAN的定位的数据库的装置包括：用于存储由pCell ID和基站导出的环境信息以及与网格单元匹配的无线LAN环境信息划分的网格单元的数据库; 网格单元确定单元，用于确定网格单元之间的信息未测量网格单元，所述信息未测量网格单元是在与所述网格单元匹配的无线LAN环境信息的参数中具有未测量信息的网格单元; 用于检查信息未测量网格单元中的未测量参数的未测量参数检查单元; 无线电波环境估计单元，用于通过基于所检查的未测量参数估计未测量信息来生成无线电波环境估计信息; 以及数据库更新单元，用于反映所确定的信息未测量网格单元中的无线电波环境估计信息。

65. 发明授权

US08605536B2 Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods 失效
标题翻译：用于复位存储器件的上电复位（POR）电路，以及相关电路，系统和方法
公开(公告)号：US08605536B2
公开(公告)日：2013-12-10
申请号：US13460862
申请日：2012-05-01
申请人： Esin Terzioglu , Balachander Ganesan , Alex Dongkyu Park , Sei Seung Yoon
发明人： Esin Terzioglu , Balachander Ganesan , Alex Dongkyu Park , Sei Seung Yoon
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/20
摘要： Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition.
摘要翻译：公开了用于重置存储器件的上电复位（POR）电路以及相关电路，系统和方法。在一个实施例中，提供了一个POR电路。 POR电路被配置为从至少一个存储器解码装置接收多个解码的地址输出作为输入。 POR电路还被配置为如果多个解码的地址输出中的任一个是有效的，则产生POR复位。结果，存储器解码装置锁存器可以被重置为已知的默认条件，以避免在外部复位可用之前在上电状态期间在存储器中引起无意的字线选择。由于POR电路可以在不需要外部复位的情况下生成POR复位，所以可以快速复位存储器解码器件，以便在上电状态后可以更快地提供存储器的可用性。

66. 发明授权

US08498169B2 Code-based differential charging of bit lines of a sense amplifier 有权
标题翻译：读出放大器的位线的基于码的差分充电
公开(公告)号：US08498169B2
公开(公告)日：2013-07-30
申请号：US13224562
申请日：2011-09-02
申请人： Hari M. Rao , Esin Terzioglu , Sei Seung Yoon
发明人： Hari M. Rao , Esin Terzioglu , Sei Seung Yoon
IPC分类号： G11C29/00 , G11C16/28
CPC分类号： G11C16/28 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.
摘要翻译：电路包括响应于存储测试码的多个锁存器的多个电容器。第一位线耦合到位单元并耦合到读出放大器。第二位线耦合到位单元并耦合到读出放大器。来自一组多个电容器的差分电荷被施加到第一位线和第二位线。基于测试代码确定多个电容器的集合，并且测试代码独立于读出放大器的输出。

67. 发明授权

US08438433B2 Registers with full scan capability 失效
标题翻译：注册全扫描功能
公开(公告)号：US08438433B2
公开(公告)日：2013-05-07
申请号：US12886620
申请日：2010-09-21
申请人： Hari M. Rao , Sei Seung Yoon , Nan Chen
发明人： Hari M. Rao , Sei Seung Yoon , Nan Chen
IPC分类号： G11C29/00
CPC分类号： G01R31/318541 , G11C11/417 , G11C29/32
摘要： A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
摘要翻译：第一锁存器和第二锁存器的扫描测试将给定扫描值耦合到第一锁存器的输入，以将第一锁存器切换到与扫描值对应的状态，将扫描值从第一锁存器解耦合以锁定第一锁存器在该状态下锁存，将锁定在该状态的第一锁存器的输出耦合到第二锁存器的输入端，以将第二锁存器切换到该状态，并且将第一锁存器的输出与第二锁存器的输入端分离在该状态下的第二个闩锁。

68. 发明申请

US20120274510A1 APPARATUS AND METHOD FOR ESTIMATING THE LOCATION OF A PORTABLE TERMINAL 审中-公开
标题翻译：估计便携式终端位置的装置和方法
公开(公告)号：US20120274510A1
公开(公告)日：2012-11-01
申请号：US13189740
申请日：2011-07-25
申请人： Seung-Yoon LEE , Do-Hyoung CHUNG , Myeong-Woo KOO
发明人： Seung-Yoon LEE , Do-Hyoung CHUNG , Myeong-Woo KOO
IPC分类号： G01S19/48
CPC分类号： G01S19/252
摘要： An apparatus and method for location estimation in a portable terminal are provided. An operation of the portable terminal includes, if a location estimation function is activated, determining whether a reference location corresponding to a cell IDentifier (ID) of a currently connected cell is prestored, determining a search frequency range of a Global Positioning System (GPS) signal using the stored reference location, and estimating a location of the portable terminal using the GPS signal detected in the search frequency range.
摘要翻译：提供了一种用于便携式终端中的位置估计的装置和方法。便携式终端的操作包括：如果位置估计功能被激活，则确定与当前连接的小区的小区标识符（ID）相对应的参考位置是否被预先存储，确定全球定位系统（GPS）的搜索频率范围，使用存储的参考位置的信号，以及使用在搜索频率范围中检测到的GPS信号来估计便携式终端的位置。

69. 发明授权

US08228714B2 Memory device for resistance-based memory applications 有权
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：US08228714B2
公开(公告)日：2012-07-24
申请号：US12206933
申请日：2008-09-09
申请人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
发明人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
IPC分类号： G11C11/00
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

70. 发明申请

US20120133048A1 SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及其制造方法及其半导体器件包括半导体器件
公开(公告)号：US20120133048A1
公开(公告)日：2012-05-31
申请号：US13235369
申请日：2011-09-17
申请人： Ho-Jin LEE , Tae-Je CHO , Dong-Hyeon JANG , Ho-Geon SONG , Se-Young JEONG , Un-Byoung KANG , Min-Seung YOON
发明人： Ho-Jin LEE , Tae-Je CHO , Dong-Hyeon JANG , Ho-Geon SONG , Se-Young JEONG , Un-Byoung KANG , Min-Seung YOON
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.
摘要翻译：在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。第二表面限定再分布沟槽。基板具有贯穿其中的通孔。半导体器件还包括设置在通孔中的贯通孔。通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。通孔还可以包括邻近阻挡层的导电连接器。半导体器件还包括形成在衬底的第二表面上的绝缘层图案。绝缘层图案限定了暴露通孔的顶表面的区域的开口。半导体器件包括设置在沟槽中并与通孔电连接的再分配层。绝缘层图案与导电连接器的区域重叠。

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