专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20070153886A1 Isolator and a modem device using the isolator 失效
标题翻译：隔离器和使用隔离器的调制解调器设备
公开(公告)号：US20070153886A1
公开(公告)日：2007-07-05
申请号：US11714856
申请日：2007-03-07
申请人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
发明人： Seigoh Yukutake , Yasuyuki Kojima , Minehiro Nemoto , Masatsugu Amishiro , Takayuki Iwasaki , Shinichiro Mitani , Katsuhiro Furukawa , Chiyoshi Kamada , Atsuo Watanabe , Takayuki Oouchi , Nobuyasu Kanekawa
IPC分类号： H04L5/16
CPC分类号： H04L25/0266 , H01L2924/0002 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L27/0002 , H04M11/06 , H01L2924/00
摘要： A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.
摘要翻译：提供一种通信系统，包括收发机和应用控制器，用于通过收发信机发送和接收信号。绝缘和分离收发器和应用控制器的隔离器包括在基板上彼此绝缘的初级和次级侧电路和用于在初级侧和第二侧之间传递信号的电容绝缘装置，同时将初级侧电路与次级侧隔离电路。

62. 发明授权

US07233534B2 Electronic circuit package 失效
标题翻译：电子电路封装
公开(公告)号：US07233534B2
公开(公告)日：2007-06-19
申请号：US11180733
申请日：2005-07-14
申请人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
发明人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
IPC分类号： G11C7/00
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
摘要翻译：一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路。

63. 发明授权

US07228372B2 Data communication system with an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices 有权
标题翻译：具有SPI总线的数据通信系统具有多个设备，其中使用对各个设备最佳的通信协议来启用数据通信
公开(公告)号：US07228372B2
公开(公告)日：2007-06-05
申请号：US11016769
申请日：2004-12-21
申请人： Kentaro Yoshimura , Wataru Nagaura , Takanori Yokoyama , Nobuyasu Kanekawa
发明人： Kentaro Yoshimura , Wataru Nagaura , Takanori Yokoyama , Nobuyasu Kanekawa
IPC分类号： G06F3/00 , G06F13/00 , H04L7/00 , H04L29/06 , H04J3/06
CPC分类号： G06F13/4291 , G06F9/54 , G06F13/102 , H04L12/40019 , H04L12/403 , H04L2012/40273
摘要： A data communication system includes a master device, a plurality of slave devices, at least either a data transmission bus which connects the master device to a plurality of slave devices to transfer data from the master device to the slave devices in synchronism with a synchronous clock signal or a data reception bus over which the master device receives data from the slave devices in synchronism with a synchronous clock signal, and Chip Select signal lines which one-to-one connect the master device to the slave devices. The data communication system also includes communication drivers for setting a physical protocol of each slave device and a communication manager to arbitrate serial communications between the master device and the slave devices. The communication manager arbitrates serial communications to slave devices by their proper physical protocols. Communication protocols such as baud rates, clock polarities, and clock phases are switched by asserted Chip Select signal lines.
摘要翻译：数据通信系统包括主设备，多个从设备，至少一个数据传输总线，其将主设备连接到多个从设备，以与同步时钟同步地将数据从主设备传送到从设备信号或数据接收总线，主设备通过该数据接收总线与同步时钟信号同步地从从设备接收数据，以及一对一将主设备连接到从设备的片选信号线。数据通信系统还包括用于设置每个从设备的物理协议的通信驱动器和通信管理器来仲裁主设备和从设备之间的串行通信。通信管理器通过其适当的物理协议仲裁到从设备的串行通信。诸如波特率，时钟极性和时钟相位之类的通信协议由断言的片选信号线切换。

64. 发明授权

US07128048B2 Control apparatus and control method for multi-cylinder engine 失效
公开(公告)号：US07128048B2
公开(公告)日：2006-10-31
申请号：US10390771
申请日：2003-03-19
申请人： Shiro Yamoaka , Toshiharu Nogi , Atsushi Shimada , Nobuyasu Kanekawa , Youichi Iihoshi
发明人： Shiro Yamoaka , Toshiharu Nogi , Atsushi Shimada , Nobuyasu Kanekawa , Youichi Iihoshi
IPC分类号： F02D41/14 , B60W10/06 , B60W50/06
CPC分类号： F02D13/0265 , B60W10/04 , B60W10/10 , B60W30/1819 , B60W2710/0616 , F02B1/12 , F02D13/0207 , F02D35/023 , F02D35/028 , F02D41/006 , F02D41/008 , F02D41/3035 , F02D41/3076 , F02D2041/001 , F02D2041/288 , Y02T10/128 , Y02T10/18 , Y02T10/47 , Y02T10/52 , Y02T10/84 , Y10T477/675 , Y10T477/68 , Y10T477/688
摘要： In a multi-cylinder engine having a compression ignition combustion mode, a vibration detecting sensor that is preferably mounted in a cylinder block or a cylinder head is used to detect a frequency and the detected frequency is appropriately analyzed to detect or estimate a cylinder pressure peak value and peak timing for each cylinder. An amount of internal EGR, a fuel injection condition, an engine speed and the like are then controlled so as to bring each of these parameters into an appropriate range thereof. The control apparatus suppresses variations in combustion states among different cylinders and different cycles arising from unit-to-unit variations or deterioration in the engine or part-to-part variations or deterioration in a component thereof.

65. 发明申请

US20050280570A1 RESOLVER/DIGITAL CONVERTER AND CONTROL APPARATUS USING THE SAME 有权
标题翻译：使用它的解决方案/数字转换器和控制装置
公开(公告)号：US20050280570A1
公开(公告)日：2005-12-22
申请号：US11211506
申请日：2005-08-26
申请人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
发明人： Nobuyasu Kanekawa , Shoji Sasaki , Katsuya Oyama , Tomonobu Koseki
IPC分类号： G01D5/244 , B60T8/88 , B60T17/18 , B62D5/04 , G01D5/20 , G05B9/02 , G05D3/12 , H03M1/10 , H03M1/64 , H03M1/12
CPC分类号： B60T8/885 , B60T2270/402 , B62D5/0481 , G01D5/2073 , G05B9/02 , H03M1/1076 , H03M1/645
摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.
摘要翻译：该解算器/数字转换器具有分解器，分解器/数字转换部分和激励信号发生器。从激励信号发生器产生的激励信号被提供给解算器，并且从分解器产生的解算器信号被提供给解算器/数字转换器。该解算器/数字转换器还具有转换触发发生器，其基于从激励信号发生器产生的激励信号产生转换触发信号，A / D转换器将从分解器产生的分解器信号转换为数字值涉及从转换触发发生器产生的转换触发信号，以及基于从A / D转换器产生的数字值来检测故障状态的计算装置。

66. 发明申请

US20050267663A1 Vehicular control system and control method 有权
标题翻译：车辆控制系统及控制方法
公开(公告)号：US20050267663A1
公开(公告)日：2005-12-01
申请号：US11072494
申请日：2005-03-07
申请人： Ken Naono , Masaaki Shimizu , Fumio Arakawa , Nobuyasu Kanekawa , Kohei Sakurai , Masatoshi Hoshino , Kentaro Yoshimura
发明人： Ken Naono , Masaaki Shimizu , Fumio Arakawa , Nobuyasu Kanekawa , Kohei Sakurai , Masatoshi Hoshino , Kentaro Yoshimura
IPC分类号： B60R16/02 , B60W10/00 , B60W10/02 , B60W10/04 , B60W10/06 , B60W10/10 , B60W10/12 , B60W10/18 , B60W10/184 , B60W10/20 , B60W10/22 , F02D45/00 , G05B13/02 , G06F17/00
CPC分类号： G05B13/024
摘要： To reduce the man-hour required in tuning control parameters, a vehicular control system of this invention comprises a user parameter input module, an external parameter input module, a plurality of objective functions, a policy setting module, and a policy node. The user parameter input module inputs a user parameter corresponding to an operation of a user. The external parameter input module inputs an external parameter resulting from an outside environment. The objective functions are set for each control characteristic respectively so as to calculate an internal parameter of each control target from the user parameter and the external parameter. The policy setting module sets policies indicating a control index of the user for the objective functions respectively. The policy node weights the objective functions on the basis of the policies, adjusts the internal parameter in accordance with the policy so that the internal parameter is optimized (minimized or maximized) among the objective functions, and issues a command to a control node corresponding to the internal parameter.
摘要翻译：为了减少调谐控制参数所需的工时，本发明的车辆控制系统包括用户参数输入模块，外部参数输入模块，多个目标功能，策略设置模块和策略节点。用户参数输入模块输入与用户的操作对应的用户参数。外部参数输入模块输入外部环境引起的外部参数。分别为每个控制特性设定目标函数，以从用户参数和外部参数计算每个控制目标的内部参数。策略设置模块分别针对目标函数设置指示用户的控制索引的策略。策略节点根据策略对目标函数进行加权，根据策略调整内部参数，使内部参数在目标函数中进行优化（最小化或最大化），并向对应的控制节点发出命令内部参数。

67. 发明申请

US20050252272A1 Resolver digital converter 有权
标题翻译：分解数字转换器
公开(公告)号：US20050252272A1
公开(公告)日：2005-11-17
申请号：US11110697
申请日：2005-04-21
申请人： Tetsuro Otsuka , Atsushi Horikoshi , Nobuyasu Kanekawa , Shoji Sasaki
发明人： Tetsuro Otsuka , Atsushi Horikoshi , Nobuyasu Kanekawa , Shoji Sasaki
IPC分类号： G01D5/245 , G01D5/244 , G01W1/18
CPC分类号： G01D5/24461 , G01D5/24457
摘要： In a resolver digital converter comprising a resolver, a resolver digital conversion part, and an excitation signal generation part, the resolver digital converter for inputting an excitation signal generated in the excitation signal generation part to the resolver and inputting resolver signals outputted from the resolver to the resolver digital conversion part, a locus in which amplitude of a sine component signal among the resolver signals sin(θ), cos(θ) outputted from the resolver is plotted as the ordinate axis and amplitude of a cosine component signal is plotted as the abscissa axis is approximated by a polygon and when the locus matches with sides of the approximated polygon, it is determined that the resolver is in a normal state and when the locus does not match, it is determined that the resolver is in a failure state.
摘要翻译：在包括分解器，分解器数字转换部分和激励信号生成部分的解算器数字转换器中，所述分解器数字转换器用于将在激励信号产生部分中产生的激励信号输入到旋转变压器，并将从旋转变压器输出的解算器信号输入到旋转变压器数字转换部分将将从分解器输出的旋转变压器信号sin（θ），cos（theta）中的正弦分量信号的幅度绘制为纵轴和余弦分量信号的幅度的轨迹被绘制为横坐标轴由多边形近似，并且当轨迹与近似多边形的边匹配时，确定解析器处于正常状态，并且当轨迹不匹配时，确定旋转变压器处于故障状态。

68. 发明授权

US06728904B2 Electronic circuit package 失效
标题翻译：电子电路封装
公开(公告)号：US06728904B2
公开(公告)日：2004-04-27
申请号：US10370518
申请日：2003-02-24
申请人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
发明人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
IPC分类号： H01L2338
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
摘要翻译：一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。布线基板可以是多层基板。优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

69. 发明授权

US6101627A Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them 失效
标题翻译：信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障
公开(公告)号：US6101627A
公开(公告)日：2000-08-08
申请号：US206153
申请日：1998-12-07
申请人： Tetsuya Shimomura , Fumio Murabayashi , Kotaro Shimamura , Nobuyasu Kanekawa , Takashi Hotta
发明人： Tetsuya Shimomura , Fumio Murabayashi , Kotaro Shimamura , Nobuyasu Kanekawa , Takashi Hotta
IPC分类号： G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F11/30 , G06F13/00 , G06F15/78 , H02H3/05 , G06F7/02 , G06F11/08
CPC分类号： G06F11/1637 , G06F11/1654 , G06F11/2025 , G06F11/2038 , G06F11/2043
摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
摘要翻译：信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。

70. 发明申请

US20140210393A1 CAPACITOR PRECHARGE CIRCUIT, MOTOR DRIVE SYSTEM, ELECTRIC POWER STEERING SYSTEM AND AIRBAG SYSTEM 审中-公开
标题翻译：电容器前置电路，电机驱动系统，电力转向系统和安全气囊系统
公开(公告)号：US20140210393A1
公开(公告)日：2014-07-31
申请号：US14238054
申请日：2012-07-11
申请人： Nobuyasu Kanekawa , Ryoichi Kobayashi , Tomonobu Koseki , Chihiro Sato , Tomishige Yatsugi , Hirofumi Kurimoto
发明人： Nobuyasu Kanekawa , Ryoichi Kobayashi , Tomonobu Koseki , Chihiro Sato , Tomishige Yatsugi , Hirofumi Kurimoto
IPC分类号： H02J7/00 , B60R21/26 , H02P29/00
CPC分类号： H02J7/007 , B60R16/02 , B60R21/017 , H02M3/07 , H02P29/40 , H02P29/68 , Y10T307/461
摘要： A loss (generation of heat) is reduced in a capacitor precharge circuit, thereby reducing the size of the circuit.The capacitor precharge circuit according to the present invention divides a power supply voltage using a switched capacitor voltage divider circuit, thereby carrying out charging while suppressing a both-terminal voltage of the capacitor that is subject to the charging (refer to FIG. 1).
摘要翻译：电容器预充电电路中的损耗（发热）降低，从而减小电路的尺寸。根据本发明的电容器预充电电路使用开关电容器分压器电路分割电源电压，从而在抑制进行充电的电容器的两端电压（参照图1）的同时进行充电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式