专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07939823B2 Method and structures for accelerated soft-error testing 有权
标题翻译：加速软错误测试的方法和结构
公开(公告)号：US07939823B2
公开(公告)日：2011-05-10
申请号：US11852353
申请日：2007-09-10
申请人： Michael S. Gordon , Kenneth P. Rodbell , Henry H. K. Tang
发明人： Michael S. Gordon , Kenneth P. Rodbell , Henry H. K. Tang
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： G01R31/2881 , G01R31/2858 , G01R31/31816 , H01L21/76825 , H01L21/84 , H01L23/53233 , H01L23/53238 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.
摘要翻译：一种集成电路，形成集成电路的方法以及用于软错误的集成电路测试的方法失败。集成电路包括：硅衬底; 形成在所述基板上的电介质层; 形成在电介质层中的导电布线，将形成在基板中的半导体器件互连到电路中的导线; 以及靠近一个或多个半导体器件的集成电路芯片中的α粒子发射区域。该方法包括将集成电路暴露于热中子的人造通量，以使α粒子发射区中的原子裂变为α粒子和其它原子。

62. 发明授权

US07923838B2 Method and structure for reducing contact resistance between silicide contact and overlying metallization 有权
标题翻译：用于降低硅化物接触和上覆金属化之间的接触电阻的方法和结构
公开(公告)号：US07923838B2
公开(公告)日：2011-04-12
申请号：US12122984
申请日：2008-05-19
申请人： Christian Lavoie , Conal E. Murray , Kenneth P. Rodbell
发明人： Christian Lavoie , Conal E. Murray , Kenneth P. Rodbell
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/28518 , H01L21/76877 , H01L21/76883 , H01L23/53209 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy).
摘要翻译：提供了其中接触开口中的接触电阻降低的半导体结构及其形成方法。这在本发明中通过用含金属锗化物的接触材料代替常规的接触冶金例如钨或金属硅化物，例如硅化镍或硅化铜，来实现。在本申请中使用的术语“含金属锗”表示纯金属锗（即MGe合金）或包含Si（即，MSiGe合金）的金属锗化物。

63. 发明申请

US20100323517A1 MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE 失效
标题翻译：铜互连结构中的微观结构修改
公开(公告)号：US20100323517A1
公开(公告)日：2010-12-23
申请号：US12869113
申请日：2010-08-26
申请人： Brett C. Baker-O'Neal , Cyril Cabral, JR. , Qiang Huang , Kenneth P. Rodbell
发明人： Brett C. Baker-O'Neal , Cyril Cabral, JR. , Qiang Huang , Kenneth P. Rodbell
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76873 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.
摘要翻译：为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。钴可以是铜 - 钴合金的形式或作为非常薄的钴层。本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

64. 发明授权

US07843063B2 Microstructure modification in copper interconnect structure 有权
标题翻译：铜互连结构中的微结构改性
公开(公告)号：US07843063B2
公开(公告)日：2010-11-30
申请号：US12031103
申请日：2008-02-14
申请人： Brett C. Baker-O'Neal , Cyril Cabral, Jr. , Qiang Huang , Kenneth P. Rodbell
发明人： Brett C. Baker-O'Neal , Cyril Cabral, Jr. , Qiang Huang , Kenneth P. Rodbell
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76877 , H01L21/76873 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.
摘要翻译：为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。钴可以是铜 - 钴合金的形式或作为非常薄的钴层。本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

65. 发明授权

US07517795B2 Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation 失效
标题翻译：在硅化物中使用离子注入，在CMOS器件中稳定Ni单硅化物薄膜
公开(公告)号：US07517795B2
公开(公告)日：2009-04-14
申请号：US11551647
申请日：2006-10-20
申请人： Roy A. Carruthers , Cedrik Y. Cole , Christophe Detavernier , Christian Lavoie , Kenneth P. Rodbell
发明人： Roy A. Carruthers , Cedrik Y. Cole , Christophe Detavernier , Christian Lavoie , Kenneth P. Rodbell
IPC分类号： H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.
摘要翻译：在后续热处理中，形成稳定的金属硅化物膜例如接触（源极/漏极或栅极）的方法基本上不附着在本发明中，能够附着在Si- 在形成金属硅化物之前，将含硅层注入到含Si层中。植入的离子稳定膜，因为发现植入物基本上防止结块或至少延迟聚集到比没有使用植入物的情况下更高的温度。

66. 发明申请

US20090059657A1 CMOS STORAGE DEVICES CONFIGURABLE IN HIGH PERFORMANCE MODE OR RADIATION TOLERANT MODE 有权
标题翻译： CMOS存储设备可配置在高性能模式或辐射容限模式
公开(公告)号：US20090059657A1
公开(公告)日：2009-03-05
申请号：US11845170
申请日：2007-08-27
申请人： Ethan H. Cannon , Michael S. Gordon , Christopher D. LeBlanc , Kenneth P. Rodbell
发明人： Ethan H. Cannon , Michael S. Gordon , Christopher D. LeBlanc , Kenneth P. Rodbell
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C11/4125 , G11C13/0004
摘要： A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline state, the material reversibly convertible between the amorphous state and the crystalline state by application of heat; an optional resistive heating element proximate to the resistor; and means for writing data to the charge storage node and means for reading data from the charge storage node.
摘要翻译：辐射耐受电路，电路结构及自主辐射事件装置保护方法。电路包括连接到电阻器的电荷存储节点，该电阻器包括具有非晶状态和结晶状态的材料，非晶状态具有比结晶状态更高的电阻，该材料可在非晶状态和结晶态之间可逆地转换通过应用热量; 靠近电阻器的可选电阻加热元件; 以及用于向电荷存储节点写入数据的装置和用于从电荷存储节点读取数据的装置。

67. 发明申请

US20080318365A1 FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING 有权
标题翻译：在芯片包装中形成ALPHA颗粒
公开(公告)号：US20080318365A1
公开(公告)日：2008-12-25
申请号：US12200352
申请日：2008-08-28
申请人： Paul Stephen Andry , Cyril Cabral, JR. , Kenneth P. Rodbell , Robert L. Wisnieff
发明人： Paul Stephen Andry , Cyril Cabral, JR. , Kenneth P. Rodbell , Robert L. Wisnieff
IPC分类号： H01L21/60
CPC分类号： H01L23/556 , H01L21/304 , H01L21/481 , H01L24/11 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/16 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/29111 , H01L2224/73204 , H01L2224/81801 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/2064 , H01L2924/3025 , H01L2224/13111 , H01L2924/00014
摘要： A structure fabrication method. First, an integrated circuit including N chip electric pads is provided electrically connected to a plurality of devices on the integrated circuit. Then, an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield is provided being exposed to a surrounding ambient at the top side but not at the bottom side. Next, the integrated circuit is bonded to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors. Next, the bottom side of the interposing shield is polished so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield. Then, N solder bumps are formed on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.
摘要翻译：一种结构制造方法。首先，将包括N个芯片电焊盘的集成电路电连接到集成电路上的多个器件。然后，设置具有顶侧和底侧并且在插入式屏蔽中具有N个电导体的插入式屏蔽件，其暴露于顶侧周围的环境而不是在底侧。接下来，集成电路接合到中间屏蔽的顶侧，使得N个芯片电极焊盘与N个导电体电接触。接下来，对中介屏蔽的底面进行抛光，以将N根电导体暴露于插入式屏蔽的底侧周围环境。然后，在中间屏蔽的抛光底面上形成N个焊料凸块，并与N个导电体电接触。

68. 发明申请

US20080311745A1 High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication 有权
标题翻译：用于pFET的高温加工兼容金属栅电极和制造方法
公开(公告)号：US20080311745A1
公开(公告)日：2008-12-18
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/44
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译：描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。这些金属的工作功能使其与当前的pFET要求兼容。例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术当Re沉积时使用材料。

69. 发明申请

US20080201681A1 COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE 有权
标题翻译：计算机程序产品用于确定相对于旅行颗粒的设计结构的停止功能
公开(公告)号：US20080201681A1
公开(公告)日：2008-08-21
申请号：US12111529
申请日：2008-04-29
申请人： Giovanni Fiorenza , Conal E. Murray , Kenneth P. Rodbell , Henry Tang
发明人： Giovanni Fiorenza , Conal E. Murray , Kenneth P. Rodbell , Henry Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/16
摘要： A computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code including an algorithm adapted to implement a method including the following steps. First, design information of the design structure is provided including a back-end-of-line layer of the integrated circuit which includes N interconnect layers, N being a positive integer. Next, each interconnect layer of the N interconnect layers is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, M being a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined.
摘要翻译：一种计算机程序产品，包括具有包含在其中的计算机可读程序代码的计算机可用介质，所述计算机可读程序代码包括适于实现包括以下步骤的方法的算法。首先，提供设计结构的设计信息，其包括包括N个互连层的集成电路的后端行层，N是正整数。接下来，N个互连层的每个互连层被分成多个像素。接下来，确定N个互连层的第一互连层中的行进粒子的第一路径。接下来，识别行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，M是正整数。接下来，确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。

70. 发明申请

US20080164584A1 METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS 失效
标题翻译：降低综合电路中软错误率的方法和结构
公开(公告)号：US20080164584A1
公开(公告)日：2008-07-10
申请号：US12051040
申请日：2008-03-19
申请人： Cyril Cabral , Michael S. Gordon , Kenneth P. Rodbell
发明人： Cyril Cabral , Michael S. Gordon , Kenneth P. Rodbell
IPC分类号： H01L23/556 , G01R31/26 , G06F17/50
CPC分类号： H01L23/556 , H01L21/76801 , H01L21/76834 , H01L21/76838 , H01L23/5329 , H01L23/53295 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05554 , H01L2224/05572 , H01L2224/05599 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/451 , H01L2224/48227 , H01L2224/48465 , H01L2224/85399 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01055 , H01L2924/01057 , H01L2924/01063 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/01092 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2224/05552
摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.
摘要翻译：降低集成电路中软错误率的结构和方法。该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式