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61. 发明授权

US07781871B2 Structure for reduction of soft error rates in integrated circuits 失效
标题翻译：降低集成电路中软错误率的结构
公开(公告)号：US07781871B2
公开(公告)日：2010-08-24
申请号：US12483364
申请日：2009-06-12
申请人： Cyril Cabral, Jr. , Michael S. Gordon , Kenneth P. Rodbell
发明人： Cyril Cabral, Jr. , Michael S. Gordon , Kenneth P. Rodbell
IPC分类号： H01L23/552
CPC分类号： H01L23/556 , H01L21/76801 , H01L21/76834 , H01L21/76838 , H01L23/5329 , H01L23/53295 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05554 , H01L2224/05572 , H01L2224/05599 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/451 , H01L2224/48227 , H01L2224/48465 , H01L2224/85399 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01055 , H01L2924/01057 , H01L2924/01063 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/01092 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2224/05552
摘要： A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.
摘要翻译：用于降低集成电路中软错误率的结构。该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

62. 发明申请

US20080308747A1 RADIATION DETECTION SCHEMES, APPARATUS AND METHODS OF TRANSMITTING RADIATION DETECTION INFORMATION TO A NETWORK 失效
标题翻译：辐射检测方案，向网络发射辐射检测信息的装置和方法
公开(公告)号：US20080308747A1
公开(公告)日：2008-12-18
申请号：US11342429
申请日：2006-01-30
申请人： Michael S. Gordon , Kenneth P. Rodbell , Robert L. Wisnieff
发明人： Michael S. Gordon , Kenneth P. Rodbell , Robert L. Wisnieff
IPC分类号： G01T3/00
CPC分类号： G01T1/04
摘要： Personal radiation detection devices, methods of obtaining radiation exposure data, and networks of personal radiation devices. The detection devices may include passive devices and active devices. The passive detection devices may have the same form factor as credit cards or be included in common types of credit card form factor sized cards. The active devices may be incorporated into common and widely distributed host devices.
摘要翻译：个人辐射检测装置，获得辐射照射数据的方法和个人辐射装置的网络。检测设备可以包括无源设备和有源设备。被动检测设备可以具有与信用卡相同的形式，或者被包括在常规类型的信用卡形状因子大小的卡中。有源器件可以并入公共和广泛分布的主机设备中。

63. 发明申请

US20080225573A1 STATIC RANDOM ACCESS MEMORY CELL WITH IMPROVED STABILITY 失效
标题翻译：静态随机访问存储单元具有改进的稳定性
公开(公告)号：US20080225573A1
公开(公告)日：2008-09-18
申请号：US12130257
申请日：2008-05-30
申请人： Azeez Bhavnagarwala , Stephen V. Kosonocky , Sampath Purushothaman , Kenneth P. Rodbell
发明人： Azeez Bhavnagarwala , Stephen V. Kosonocky , Sampath Purushothaman , Kenneth P. Rodbell
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , Y10S257/903
摘要： A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.
摘要翻译：存储单元包括字线，具有第一输入和第一输出的第一数字逆变器以及具有第二输入和第二输出的第二数字反相器。此外，存储单元还包括将第一输出连接到第二输入的第一反馈连接和将第二输出连接到第一输入的第二反馈连接。第一反馈连接包括第一电阻元件，第二反馈连接包括第二电阻元件。更重要的是，每个数字逆变器都有相关的电容。存储单元被配置为使得读取存储器单元包括将读取电压脉冲施加到字线。此外，第一和第二电阻元件被配置为使得第一和第二反馈连接具有比施加的读取电压脉冲更长的电阻 - 电容感应延迟。

64. 发明授权

US07183758B2 Automatic exchange of degraders in accelerated testing of computer chips 失效
标题翻译：自动交换降解器加速电脑芯片测试
公开(公告)号：US07183758B2
公开(公告)日：2007-02-27
申请号：US10734694
申请日：2003-12-12
申请人： Carl E. Bohnenkamp , Ethan H. Cannon , Ethan W. Cascio , Michael S. Gordon , Kenneth P. Rodbell , Theodore H. Zabel
发明人： Carl E. Bohnenkamp , Ethan H. Cannon , Ethan W. Cascio , Michael S. Gordon , Kenneth P. Rodbell , Theodore H. Zabel
IPC分类号： G01R31/28
CPC分类号： H01L21/68764 , H01L21/67213 , H01L21/68771
摘要： Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.
摘要翻译：根据本发明的至少一个目前优选的实施例解决的问题是：在物理交换降解器（先前由手工完成）所花费的时间上的改进; 这样做的安全性，因为降解物变得高度放射性; 如果加速器可以连续运行，可能改善能量分辨率和光束稳定性; 并对射束电流，光束位置和稳定性进行现场监测。特别考虑的是自动而不是手动地以安全的方式改变降解器的方法和装置。

65. 发明授权

US06986078B2 Optimization of storage and power consumption with soft error predictor-corrector 失效
标题翻译：使用软错误预测器校正器优化存储和功耗
公开(公告)号：US06986078B2
公开(公告)日：2006-01-10
申请号：US10213690
申请日：2002-08-07
申请人： Kenneth P. Rodbell , Henry H. K. Tang , Robert M. Trepp , Robert Chi-Foon Wong
发明人： Kenneth P. Rodbell , Henry H. K. Tang , Robert M. Trepp , Robert Chi-Foon Wong
IPC分类号： G06F11/00
CPC分类号： H04L1/0001
摘要： A method and system for mitigating the impact of radiation induced in a data processor incorporating integrated circuits. The method comprises the steps of determining the location of the data processor, determining a set of radiation sources and intensities at that location, and estimating the soft error rate of the data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value. The data processor is modified (either hardware or software) in response to the estimate value at times the estimate value exceeds a predetermined value.
摘要翻译：一种用于减轻包含集成电路的数据处理器中引起的辐射影响的方法和系统。该方法包括以下步骤：确定数据处理器的位置，确定该位置处的一组辐射源和强度，以及根据确定的所述集成的辐射强度和几何特性来估计数据处理器的软错误率电路提供估计值。数据处理器在估计值超过预定值的时候响应于估计值被修改（硬件或软件）。

66. 发明授权

US06946716B2 Electroplated interconnection structures on integrated circuit chips 有权
标题翻译：集成电路芯片上的电镀互连结构
公开(公告)号：US06946716B2
公开(公告)日：2005-09-20
申请号：US10773434
申请日：2004-02-09
申请人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： H01L21/288 , H01L21/768 , H01L29/00
CPC分类号： C25D3/38 , C25D5/022 , H01L21/2885 , H01L21/76877 , H01L21/76885
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超量填充特征的能力是独一无二的，优于其他沉积方法。以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

67. 发明授权

US06836106B1 Apparatus and method for testing semiconductors 失效
标题翻译：用于半导体测试的装置和方法
公开(公告)号：US06836106B1
公开(公告)日：2004-12-28
申请号：US10668561
申请日：2003-09-23
申请人： Kevin H. Brelsford , Ronald G. Filippi, Jr. , Kenneth P. Rodbell , Ping-Chuan Wang
发明人： Kevin H. Brelsford , Ronald G. Filippi, Jr. , Kenneth P. Rodbell , Ping-Chuan Wang
IPC分类号： G01R3126
CPC分类号： G11C29/56 , G01R31/2858 , G11C29/1201 , G11C2029/5602
摘要： A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.
摘要翻译：用于测试半导体的测试电路包括多个至少第一导体和第二导体。第一和第二导体通过多个导电通孔可操作地连接在一起以形成交替的第一和第二导体的开链。包括多个导电抽头，每个抽头在第一端连接到对应的第一导体。测试电路还包括多个开关电路，每个开关电路可操作地连接到对应的一个导电抽头的第二端。响应于呈现给开关电路的至少一个控制信号，每个开关电路可配置为有选择地将对应的导电抽头连接到至少第一总线和第二总线中的一个，第一和第二总线连接到第一和第二总线第二接合垫。

68. 发明授权

US06792075B2 Method and apparatus for thin film thickness mapping 有权
标题翻译：用于薄膜厚度测绘的方法和装置
公开(公告)号：US06792075B2
公开(公告)日：2004-09-14
申请号：US10225534
申请日：2002-08-21
申请人： Krzysztof J. Kozaczek , David S. Kurtz , Paul R. Moran , Roger I. Martin , Patrick W. Dehaven , Kenneth P. Rodbell , Sandra G. Malhotra
发明人： Krzysztof J. Kozaczek , David S. Kurtz , Paul R. Moran , Roger I. Martin , Patrick W. Dehaven , Kenneth P. Rodbell , Sandra G. Malhotra
IPC分类号： G01N2320
CPC分类号： G01N23/20 , G01B15/02
摘要： An apparatus and method for mapping film thickness of one or more textured polycrystalline thin films. Multiple sample films of known thickness are provided. Each sample film is irradiated by x-ray at a measurement point to generate a diffraction image that captures a plurality of diffraction arcs. Texture information (i.e., pole densities) of the sample film, is calculated based on incomplete pole figures collected on the diffraction image and used to correct the x-ray diffraction intensities from such sample. The corrected diffraction intensities are integrated for each sample film, and then used for constructing a calibration curve that correlates diffraction intensities with respective known film thickness of the sample films. The film thickness of a textured polycrystalline thin film of unknown thickness can therefore be mapped on such calibration curve, using a corrected and integrated diffraction intensity obtained for such thin film of unknown thickness.
摘要翻译：一种用于映射一个或多个纹理多晶薄膜的膜厚度的装置和方法。提供了已知厚度的多个样品膜。每个样品膜在测量点用X射线照射，以产生捕获多个衍射弧的衍射图像。基于在衍射图像上收集的不完全的极数计算样品膜的纹理信息（即极点密度），并用于校正这些样品的X射线衍射强度。对每个样品膜整合校正的衍射强度，然后用于构建将衍射强度与样品膜的已知膜厚度相关联的校准曲线。因此，可以使用未知厚度的薄膜获得的校正和积分的衍射强度，将这种具有未知厚度的纹理多晶薄膜的膜厚度映射到这种校准曲线上。

69. 发明授权

US5434385A Dual channel D.C. low noise measurement system and test methodology 失效
标题翻译：双通道D.C.低噪声测量系统和测试方法
公开(公告)号：US5434385A
公开(公告)日：1995-07-18
申请号：US970370
申请日：1992-11-02
申请人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
发明人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
IPC分类号： G01R31/26 , G01R29/26 , H01L21/66 , F27D11/02 , H02H7/04 , H05B11/00
CPC分类号： G01R29/26
摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.
摘要翻译：具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。偏置电路和电池组还在系统外壳内设置有单独的外壳。

70. 发明授权

US4954142A Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor 失效
标题翻译：电子部件基板的化学机械研磨方法及研磨用浆料的方法
公开(公告)号：US4954142A
公开(公告)日：1990-09-04
申请号：US285435
申请日：1989-03-07
申请人： Jeffrey W. Carr , Lawrence D. David , William L. Guthrie , Frank B. Kaufman , William J. Patrick , Kenneth P. Rodbell , Robert W. Pasco , Anton Nenadic
发明人： Jeffrey W. Carr , Lawrence D. David , William L. Guthrie , Frank B. Kaufman , William J. Patrick , Kenneth P. Rodbell , Robert W. Pasco , Anton Nenadic
IPC分类号： B24B37/00 , C09G1/02 , H01L21/304 , H01L21/306 , H01L21/48
CPC分类号： H01L21/4871 , C09G1/02 , H01L21/4864
摘要： Disclosed is a method of chem-mech polishing an electronic component substrate. The method includes the following steps;obtaining a substrate having at least two features thereon or therein which have a different etch rate with respect to a particular etchant; andcontacting the substrate with a polishing pad while contacting the substrate with a slurry containing the etchant wherein the slurry includes abrasive particles, a transition metal chelated salt and a solvent for the salt.The chem-mech polishing causes the at least two features to be substantially coplanar. Also disclosed is the chem-mech polishing slurry.
摘要翻译：公开了电子部件基板的化学研磨方法。该方法包括以下步骤：获得其上具有至少两个特征的衬底，其中相对于特定蚀刻剂具有不同的蚀刻速率; 以及使所述基板与抛光垫接触，同时使所述基板与含有所述蚀刻剂的浆料接触，其中所述浆料包括磨料颗粒，过渡金属螯合盐和所述盐的溶剂。化学铣削使得至少两个特征基本上共面。还公开了化学研磨浆料。

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