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61. 发明申请

US20080137458A1 Open digit line array architecture for a memory array 有权
标题翻译：用于存储器阵列的开放数字线阵列架构
公开(公告)号：US20080137458A1
公开(公告)日：2008-06-12
申请号：US12009521
申请日：2008-01-18
申请人： Sei Seung Yoon , Charles L. Ingalls , David Pinney , Howard C. Kirsch
发明人： Sei Seung Yoon , Charles L. Ingalls , David Pinney , Howard C. Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
摘要翻译：一种用于感测由存储器单元存储的数据状态的系统和方法，包括将第一数字线和第二数字线耦合到预充电电压，并进一步将存储单元耦合到第一数字线。除了第一和第二数字线之外的至少一个数字线被驱动到参考电压电平，并且至少一个数字线耦合到第二数字线以在第二数字线中建立参考电压。在第一数字线和第二数字线之间感测到电压差，并且响应地锁存基于电压差的数据状态。

62. 发明授权

US07023751B2 Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage 有权
标题翻译：减少存取晶体管子阈值泄漏降低DRAM刷新功率的方法和电路
公开(公告)号：US07023751B2
公开(公告)日：2006-04-04
申请号：US11040959
申请日：2005-01-19
申请人： Howard C. Kirsch
发明人： Howard C. Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4067 , G11C2211/4068
摘要： The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.
摘要翻译：通过将有效数字线偏置为轻微的正电压来降低DRAM的所需刷新率，以减少未被访问的存储器单元中的存取晶体管的次阈值电流泄漏。轻微的正电压由电压调节器电路提供，该电压调节器电路使用在阱中制造的一个或多个双极晶体管，其将双极晶体管与衬底的其余部分电隔离。由电压调节器提供的电压优选地通过用来自电压调节器的电压为DRAM中的每个n检测放大器供电而耦合到存取晶体管。

63. 发明授权

US06934208B2 Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays 有权
标题翻译：用于由不同存储器阵列的列共享的限流泄放装置的装置和方法
公开(公告)号：US06934208B2
公开(公告)日：2005-08-23
申请号：US10309572
申请日：2002-12-03
申请人： J. Wayne Thompson , George B. Raad , Howard C. Kirsch
发明人： J. Wayne Thompson , George B. Raad , Howard C. Kirsch
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C7/12 , G11C2207/005
摘要： Apparatus and method for a current limiting bleeder device that is shared between columns of different memory arrays and limits a current load on a voltage supply to prevent failure of an otherwise repairable memory device. The memory device includes first and second memory arrays having memory cells arranged in rows and columns where each of the columns of the first and second memory arrays have a equilibration circuit to precharge the respective column. A bleeder device is coupled to a precharge voltage supply and further coupled to at least one equilibration circuit of a column in the first memory array and to at least one equilibration circuit of a column in the second memory array to limit the current drawn by the equilibration circuits from the precharge voltage supply.
摘要翻译：用于限流放电器件的装置和方法，其在不同存储器阵列的列之间共享并且限制电压源上的电流负载，以防止另外可修复的存储器件的故障。存储器件包括具有以行和列排列的存储单元的第一和第二存储器阵列，其中第一和第二存储器阵列的每个列具有用于对各个列进行预充电的平衡电路。放电器件耦合到预充电电压源，并且还耦合到第一存储器阵列中的列的至少一个平衡电路以及第二存储器阵列中的列的至少一个平衡电路，以限制由平衡引起的电流电路从预充电电压供应。

64. 发明授权

US06836427B2 System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems 失效
标题翻译：用于抵消开放数字阵列动态随机存取存储器系统中的电压干扰的系统和方法
公开(公告)号：US06836427B2
公开(公告)日：2004-12-28
申请号：US10163404
申请日：2002-06-05
申请人： Huy T. Vo , Charles L. Ingalls , Howard C. Kirsch
发明人： Huy T. Vo , Charles L. Ingalls , Howard C. Kirsch
IPC分类号： G11C1124
CPC分类号： G11C7/02 , G11C7/12 , G11C11/4094
摘要： The disclosed system and method introduce voltage disturbances into a reference sub-array to offset voltage disturbances occurring in an active sub-array. The disclosed system and method connect extra, unused rows of memory cells to currently unused digitlines in the reference sub-array to cause surges that create voltage disturbances like those occurring in the active sub-array as a consequence of rows of memory cells in the active sub-array being connected to the active digitlines. As a result, when the sense amplifiers compare the voltages received on the active digitlines and the reference digitlines, the effects of the voltage disturbances on the active and reference digitlines lines offset each other.
摘要翻译：所公开的系统和方法将电压干扰引入到参考子阵列中以消除在有源子阵列中出现的电压干扰。所公开的系统和方法将额外的未使用的存储单元行连接到参考子阵列中的当前未使用的数字线，以引起诸如在有源子阵列中发生的电压扰动的浪涌，这是由于活动中的存储器单元的行的结果子阵列连接到活动数字线。结果，当读出放大器比较在有源数字线和参考数字线上接收的电压时，电压扰动对有源和参考数字线的影响彼此抵消。

65. 发明授权

US06806137B2 Trench buried bit line memory devices and methods thereof 有权
标题翻译：沟槽掩埋位线存储器件及其方法
公开(公告)号：US06806137B2
公开(公告)日：2004-10-19
申请号：US10705707
申请日：2003-11-11
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译：诸如6F 2存储器件的存储器件包括大致平行于并沿着有源区的相关带形成的隔离沟槽。导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

66. 发明授权

US06738301B2 Method and system for accelerating coupling of digital signals 有权
标题翻译：加速数字信号耦合的方法和系统
公开(公告)号：US06738301B2
公开(公告)日：2004-05-18
申请号：US10232421
申请日：2002-08-29
申请人： Howard C. Kirsch
发明人： Howard C. Kirsch
IPC分类号： G11C700
CPC分类号： G11C7/1096 , G11C7/1048 , G11C7/1078
摘要： A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as VCC. Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.
摘要翻译：用于通过存储器阵列的I / O线耦合读取数据信号和写入数据信号的系统和方法。预充电电路将交变信号线预充电到高和低预充电电压。连接到已经预充电的每个I / O线的加速高电平检测到I / O线的电压在预充电低电压之上的增加。然后，加速高电路将I / O线驱动到高电压，例如VCC。类似地，耦合到已经预充电的每个I / O线的加速低电平检测到I / O线的电压降低到预充电高电压以下。加速低电压然后将I / O线驱动到低电压，例如接地。

67. 发明授权

US06734482B1 Trench buried bit line memory devices 有权
标题翻译：沟槽埋线位线存储器件
公开(公告)号：US06734482B1
公开(公告)日：2004-05-11
申请号：US10295106
申请日：2002-11-15
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译：诸如6F 2存储器件的存储器件包括大致平行于并沿着有源区的相关带形成的隔离沟槽。导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

68. 发明授权

US06327215B1 Local bit switch decode circuit and method 有权
标题翻译：本地位开关解码电路及方法
公开(公告)号：US06327215B1
公开(公告)日：2001-12-04
申请号：US09670405
申请日：2000-09-28
申请人： Luigi Ternullo, Jr. , Howard C. Kirsch
发明人： Luigi Ternullo, Jr. , Howard C. Kirsch
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097
摘要： A local bit switch selecting circuit and method for systems having a first number of banks of sense amplifiers with a second number of sense amplifiers in each sense amplifier bank. The bit switch selecting circuit and method use a single N channel field effect transistor in each sense amplifier bank. This provides bit switch selecting capability while significantly reducing the number of devices and chip area required.
摘要翻译：一种用于具有在每个读出放大器组中具有第二数量的读出放大器的第一数量的读出放大器组的系统的本地位开关选择电路和方法。位开关选择电路和方法在每个读出放大器组中使用单个N沟道场效应晶体管。这提供了位开关选择能力，同时显着减少了所需的器件数量和芯片面积。

69. 发明授权

US06300795B1 Multiple-bit, current mode data bus 有权
公开(公告)号：US06300795B1
公开(公告)日：2001-10-09
申请号：US09709598
申请日：2000-11-13
申请人： Howard C. Kirsch , Ena Ku
发明人： Howard C. Kirsch , Ena Ku
IPC分类号： H03K1902
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： A current mode data communication system is disclosed. The current mode data communication system has a transmitter to simultaneously transmit two digital data bits. The two digital data bits are combined to form a current mode signal. The current mode signal has a first positive current, a second positive current, a first negative current and a first positive current. The current mode signal will be transmitted on a double bit current mode bus. Further the current mode communication system has a receiver coupled to the double bit current mode bus to receive the current mode signal and convert the current mode signal to a unextracted form of the two digital data bits. The output of the receiver is connected to a data extractor circuit extract the two digital data bits for the unextracted form of the two digital data bits.

70. 发明授权

US06275067B1 Multiple-bit, current mode data bus 失效
标题翻译：多位，电流模式数据总线
公开(公告)号：US06275067B1
公开(公告)日：2001-08-14
申请号：US09709591
申请日：2000-11-13
申请人： Howard C. Kirsch , Ena Ku
发明人： Howard C. Kirsch , Ena Ku
IPC分类号： H03K19175
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： A current mode data communication system is disclosed. The current mode data communication system has a transmitter to simultaneously transmit two digital data bits. The two digital data bits are combined to form a current mode signal. The current mode signal has a first positive current, a second positive current, a first negative current and a first positive current. The current mode signal will be transmitted on a double bit current mode bus. Further the current mode communication system has a receiver coupled to the double bit current mode bus to receive the current mode signal and convert the current mode signal to a unextracted form of the two digital data bits. The output of the receiver is connected to a data extractor circuit extract the two digital data bits for the unextracted form of the two digital data bits.
摘要翻译：公开了一种当前模式数据通信系统。当前模式数据通信系统具有发送器以同时发送两个数字数据位。两个数字数据位被组合以形成电流模式信号。电流模式信号具有第一正电流，第二正电流，第一负电流和第一正电流。电流模式信号将在双位电流模式总线上传输。此外，电流模式通信系统具有耦合到双位电流模式总线的接收器，以接收当前模式信号并将当前模式信号转换为两个数字数据位的未提取形式。接收机的输出端连接到数据提取器电路，为两个数字数据位的未提取形式提取两个数字数据位。

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