专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07221788B2 Method of inspecting a mask or reticle for detecting a defect, and mask or reticle inspection system 有权
标题翻译：检查掩模或掩模版以检测缺陷的方法，以及掩模或掩模版检查系统
公开(公告)号：US07221788B2
公开(公告)日：2007-05-22
申请号：US10611067
申请日：2003-07-01
申请人： Steffen Schulze , Henning Haffner
发明人： Steffen Schulze , Henning Haffner
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： A method of inspecting a mask or reticle, the mask or reticle being provided with a pattern to be transferred onto a semiconductor wafer, the pattern having a defect, includes the step of creating a plurality of logical zones and uniquely associating each of said logical zones with a surface area of said pattern. Then, an inspection rule representing a characteristic sensitivity for detecting a defect is associated with each of said logical zones. An image of said pattern is then recorded and compared with a reference image of an ideal pattern for locating a defect within said pattern. One of said logical zones is then identified with said located defect and that inspection rule which is associated with said identified logical zone is retrieved from a memory. The inspection rule is then applied to a characteristic of said defect for determining, whether said defect is to be repaired. A signal can be issued in response to said determination.
摘要翻译：一种检查掩模或掩模版的方法，所述掩模或掩模版具有要转印到半导体晶片上的图案，所述图案具有缺陷，所述方法包括以下步骤：创建多个逻辑区并将每个所述逻辑区域具有所述图案的表面积。然后，表示用于检测缺陷的特征灵敏度的检查规则与每个所述逻辑区域相关联。然后记录所述图案的图像，并与用于定位所述图案内的缺陷的理想图案的参考图像进行比较。然后用所述定位的缺陷识别所述逻辑区域中的一个，并且从存储器检索与所述识别的逻辑区域相关联的检查规则。然后将检查规则应用于所述缺陷的特征，以确定是否修复所述缺陷。可以响应于所述确定而发出信号。

62. 发明授权

US07094674B2 Method for production of contacts on a wafer 有权
公开(公告)号：US07094674B2
公开(公告)日：2006-08-22
申请号：US10739477
申请日：2003-12-18
申请人： Werner Graf , Henning Haffner , Johannes Kowalewski , Lars Heineck
发明人： Werner Graf , Henning Haffner , Johannes Kowalewski , Lars Heineck
IPC分类号： H01L21/44
CPC分类号： H01L27/10888 , H01L21/76897
摘要： The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

63. 发明授权

US07056628B2 Mask for projecting a structure pattern onto a semiconductor substrate 失效
标题翻译：用于将结构图案投影到半导体衬底上的掩模
公开(公告)号：US07056628B2
公开(公告)日：2006-06-06
申请号：US10653537
申请日：2003-09-02
申请人： Shahid Butt , Henning Haffner
发明人： Shahid Butt , Henning Haffner
IPC分类号： G01F9/00
CPC分类号： G03F1/32 , G03F1/36
摘要： A mask is configured for projecting a structure pattern onto a semiconductor substrate in an exposure unit. The exposure unit has a minimum resolution limit for projecting the structure pattern onto the semiconductor substrate. The mask has a substrate, at least one raised first structure element on the substrate which has a lateral extent which is at least the minimum lateral extent that can be attained by the exposure unit, a configuration second raised structure elements which are arranged in an area surrounding the at least one first structure element on the substrate in the form of a matrix with a row spacing and a column spacing, whose shape and size are essentially identical to one another, and which have a respective lateral extent that is less than the minimum resolution limit of the exposure unit.
摘要翻译：掩模被配置为在曝光单元中将结构图案投影到半导体衬底上。曝光单元具有用于将结构图案投影到半导体衬底上的最小分辨率限制。所述掩模具有衬底，所述衬底上至少有一个凸起的第一结构元件，其具有至少可由曝光单元获得的最小横向范围的横向范围;布置在区域中的构造的第二凸起结构元件围绕基板上的至少一个第一结构元件以矩阵的形式具有行间距和列间距，其形状和尺寸彼此基本相同，并且具有小于最小值的相应横向范围曝光单位的分辨率限制。

64. 发明申请

US20050125164A1 Method for dynamically monitoring a reticle 有权
标题翻译：动态监控光罩的方法
公开(公告)号：US20050125164A1
公开(公告)日：2005-06-09
申请号：US10984797
申请日：2004-11-10
申请人： Henning Haffner , Karin Eggers , Norbert Haase , Andreas Frangen , Carmen Jaehnert
发明人： Henning Haffner , Karin Eggers , Norbert Haase , Andreas Frangen , Carmen Jaehnert
IPC分类号： G01B5/28 , G01B5/30 , G01N21/956 , G03F1/00 , G03F7/20
CPC分类号： G01N21/95692 , G01N2021/95676 , G03F1/84
摘要： The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle deposits or electrostatically induced damage, and energy load, including the associated changes to the reticle material and surface characteristics. Different surface distributions of the absorber layer as well as characteristics of the exposure system, such as N2 purging of the projection lens/reticle area in order to reduce contamination and recrystallization on optically active surfaces are considered.
摘要翻译：动态监测掩模版的方法包括对机械载荷（包括颗粒沉积物或静电诱发的损伤）以及能量负载（包括对掩模版材料的相关变化和表面特性）的预防性宏观监测和缺陷检查。考虑吸收层的不同表面分布以及曝光系统的特性，例如投影透镜/掩模版区域的N 2清洗，以减少光学活性表面上的污染和重结晶。

65. 发明授权

US06426269B1 Dummy feature reduction using optical proximity effect correction 失效
标题翻译：使用光学邻近效应校正的虚拟特征降低
公开(公告)号：US06426269B1
公开(公告)日：2002-07-30
申请号：US09422634
申请日：1999-10-21
申请人： Henning Haffner , Heinz Hoenigschmid , Donald J. Samuels
发明人： Henning Haffner , Heinz Hoenigschmid , Donald J. Samuels
IPC分类号： H01L2176
CPC分类号： G03F7/70441 , G03F1/36
摘要： A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions. The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions. The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.
摘要翻译：一种用于采用该方法的方法和系统，用于提供用于校正半导体电路晶片上的图案线的失真的修改的光学邻近校正（OPC）。该方法包括制备具有一个或多个图案区域的掩模，并从掩模制造半导体电路晶片。图案区域包括与掩模上的其它非边缘图案区域相邻的一个或多个非边缘图案区域。图案区域还包括位于不具有其它非边缘图案区域的掩模上的区域附近或附近的一个或多个边缘图案区域。边缘图案区域具有计算的宽度，以使由其形成的半导体电路晶片上的一个或多个图案线与由非边缘图案区域形成的半导体电路晶片上的一个或多个图案线之间的尺寸变化最小化。计算任何两个图案区域之间的距离，以使从边缘图案区域形成的一个或多个图案线和由非边缘图案区域形成的一个或多个图案线之间的尺寸变化最小化。上述制造步骤包括从具有由非边缘图案区形成的图案线的掩模制造半导体电路晶片，并且具有由边缘图案区形成的图案线，其中从非边缘区域形成的图案线被允许它们之间的距离不同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式