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    • 63. 发明申请
    • FILTERS FOR MULTI-BAND WIRELESS DEVICE
    • 多带无线设备滤波器
    • WO2014043271A1
    • 2014-03-20
    • PCT/US2013/059309
    • 2013-09-11
    • QUALCOMM INCORPORATED
    • CABANILLAS, JoseHADJICHRISTOS, AristoteleKRISTENSEN, Per O.PUNTAMBEKAR, Mohan V.
    • H03H7/46H03H11/34H04B1/00H04B1/18H04B1/707H04B1/48H01P1/213H03H7/38H03H11/30
    • H03H11/344H01P1/213H03H7/465H03H11/30H03H2007/386H04B1/0458
    • Techniques to implement a filter for a selected signal path by reusing a circuit component in an unselected signal path are disclosed. In an exemplary design, an apparatus includes first, second, and third circuits (580a, 580b, 560a). The first circuit (580a) passes a first radio frequency (RF) signal to an antenna (598) when a first signal path (522a) is selected. The second circuit (580b) passes a second RF signal to the antenna (598) when a second signal path (522b) is selected. The third circuit (560a) is selectively coupled to the first circuit (580a), e.g., via a switch (562a). The first and third circuits (580a, 560a) form a filter for the second RF signal (e.g., to attenuate a harmonic of the second RF signal) when the second signal path (522b) is selected and the first signal path (522a) is unselected. The first circuit may include a series inductor, and the third circuit may include a shunt capacitor.
    • 公开了通过重新使用未选信号路径中的电路部件来实现所选信号路径的滤波器的技术。 在示例性设计中,装置包括第一,第二和第三电路(580a,580b,560a)。 当选择第一信号路径(522a)时,第一电路(580a)将第一射频(RF)信号传递到天线(598)。 当选择第二信号路径(522b)时,第二电路(580b)将第二RF信号传递到天线(598)。 第三电路(560a)例如经由开关(562a)选择性地耦合到第一电路(580a)。 当选择第二信号路径(522b)并且第一信号路径(522a)是第一信号路径(522a)时,第一和第三电路(580a,560a)形成用于第二RF信号的滤波器(例如,衰减第二RF信号的谐波) 未选中。 第一电路可以包括串联电感器,并且第三电路可以包括并联电容器。
    • 64. 发明申请
    • RECEIVER ARCHITECTURE
    • 接收体系结构
    • WO2014043270A1
    • 2014-03-20
    • PCT/US2013/059308
    • 2013-09-11
    • QUALCOMM INCORPORATED
    • CHANG, Li-ChungGUDEM, Prasad Srinivasa SivaBOSSU, FredericHOLENSTEIN, Christian
    • H04B1/00H04B1/28
    • H04J3/00H03F3/72H04B1/0064H04B1/0071
    • A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.
    • 公开了用于载波聚合的接收机架构。 在示例性设计中,装置(例如,无线装置,电路模块等)包括多个低噪声放大器(LNA),多个开关和至少一个下变频器。 LNA接收和放大至少一个输入射频(RF)信号并提供至少一个放大的RF信号。 开关耦合到多个LNA的输出端。 所述至少一个下变频器耦合到所述多个开关,对所述至少一个放大的RF信号进行下变频,并提供至少一个下变频信号。 交换机减少了通过多个接收天线支持在多组载波上接收传输所需的下变频器的数量。 LNA和交换机可以在至少一个前端模块或后端模块上实现。 下变频器在后端模块上实现。
    • 65. 发明申请
    • MULTI-CASCODE AMPLIFIER BIAS TECHNIQUES
    • 多芯片放大器偏置技术
    • WO2014026030A1
    • 2014-02-13
    • PCT/US2013/054187
    • 2013-08-08
    • QUALCOMM INCORPORATED
    • SU, WenjunNARATHONG, ChiewcharnYIN, GuangmingHADJICHRISTOS, Aristotele
    • H03F1/22H03F3/193
    • H03F1/223H03F3/193
    • Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, which enables accurate biasing of the transistors in the multi-cascode amplifier. In a further aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may advantageously be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.
    • 用于产生多共源共栅放大器偏置电压的技术。 在一方面,提供了多共源共栅偏压网络,偏置网络中的每个晶体管是多级共源共栅放大器中对应的晶体管的复制品,其使多级共源共栅放大器中的晶体管能够精确偏置。 在另一方面,用于多重共源共栅放大器的电压源与用于复制偏压网络的电压源分开设置,以有利地将放大器电压源的偏差与偏压网络电压电源分离。 在另一方面,多并联放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。 由于放大器的增益取决于共源共栅放大器的偏置电压,所以可以以这种方式有利地调节放大器的增益,而不将可变增益元件直接引入放大器信号路径。
    • 70. 发明申请
    • TECHNIQUES FOR PGA LINEARITY
    • PGA线性的技术
    • WO2013090851A1
    • 2013-06-20
    • PCT/US2012/069948
    • 2012-12-14
    • QUALCOMM INCORPORATED
    • XIE, Weijun Serena
    • H03F3/45H03F1/32H03G1/00H03G3/00
    • H03F3/45475H03F1/3211H03F2203/45522H03F2203/45534H03F2203/45591H03F2203/45616H03G1/0088H03G3/001
    • Techniques for designing a highly linear programmable gain amplifier, PGA. In an aspect, the PGA includes a plurality of feedback switches selectively coupling an output (von, Vop) of an operational amplifier, op amp (OA), to an input (Vp, Vn) of the op amp (OA) via a corresponding series-coupled feedback resistance. The PGA may further include a plurality of input switches selectively coupling an input (vp, Vn) of the op amp (OA) to a PGA input voltage (Vinp, Vinn) via a corresponding series-coupled input resistance. The switches are designed such that the ratio of on-resistances between any two switches is substantially equal to the ratio of the corresponding series-coupled resistances. In an exemplary embodiment, transistors implementing the switches may be accordingly sized to implement the desired on-resistance ratios.
    • 设计高度线性可编程增益放大器PGA的技术。 在一方面,PGA包括多个反馈开关,其选择性地将运算放大器(op)(OA)的输出(von,Vop)与运算放大器(OA)的输入(Vp,Vn)经由相应的 串联反馈电阻。 PGA还可以包括多个输入开关,其经由相应的串联耦合输入电阻选择性地将运算放大器(OA)的输入(vp,Vn)耦合到PGA输入电压(Vinp,Vinn)。 开关被设计成使得任何两个开关之间的导通电阻的比率基本上等于相应串联电阻的比率。 在示例性实施例中,实现开关的晶体管的尺寸可以相应地大小以实现期望的导通电阻比。