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61. 发明授权

US4857780A High withstand voltage output 失效
标题翻译：高耐压输出
公开(公告)号：US4857780A
公开(公告)日：1989-08-15
申请号：US245999
申请日：1988-09-14
申请人： Hiromichi Kuwano
发明人： Hiromichi Kuwano
IPC分类号： H03K17/08 , H03K17/10 , H03K17/56 , H03K17/567 , H03K19/003 , H03K19/013 , H03K19/0944
CPC分类号： H03K17/102 , H03K17/10 , H03K19/00307 , H03K19/0136 , H03K19/09448
摘要： A high withstand voltage output circuit has a pull-up constant current source and transistor connected in series between the grounding side and supply voltage side wherein the breakdown voltage of the constant current source is set higher than the pinch-off voltage of the transistor.
摘要翻译：高耐压输出电路具有在接地侧和电源电压侧串联连接的上拉恒流源和晶体管，其中恒定电流源的击穿电压被设定为高于晶体管的截止电压。

62. 发明授权

US09819209B2 Contactless charging of BLUETOOTH other wireless headsets 有权
公开(公告)号：US09819209B2
公开(公告)日：2017-11-14
申请号：US13353145
申请日：2012-01-18
申请人： Steven E. Hunt , Mathew Jacob
发明人： Steven E. Hunt , Mathew Jacob
IPC分类号： B60L1/00 , B60L3/00 , H02G3/00 , H02J7/02 , H02J7/00 , H01F38/14
CPC分类号： H02J7/025 , H01F38/14 , H02J7/00 , H02J7/0044 , H02J50/10 , H02J50/40
摘要： An apparatus includes an adapter having a charging unit defining a space configured to receive a wireless headset. The charging unit includes transmit circuitry configured to wirelessly transmit power to the wireless headset when the wireless headset is inserted into the space of the charging unit. At least a portion of the adapter is configured to be inserted into an auxiliary or accessory power socket of a vehicle. The power socket could represent a cigarette lighter holster.

63. 发明申请

US20150229124A1 DYNAMIC CURRENT PULL-DOWN FOR VOLTAGE REGULATOR 有权
标题翻译：电压调节器的动态电流下拉
公开(公告)号：US20150229124A1
公开(公告)日：2015-08-13
申请号：US14176910
申请日：2014-02-10
申请人： Texas Instruments Incorporated
发明人： Donghwi Kim , Patrick Michael Teterud
IPC分类号： H02H9/04 , H02H9/00
CPC分类号： G05F1/571
摘要： A circuit includes a comparator that monitors a transient with respect to a predetermined threshold at the output of a voltage regulator and generates a compensation signal if the transient exceeds the predetermined threshold. A dynamic current pull-down block is triggered from the compensation signal of the comparator and operative with an output stage of the voltage regulator to mitigate the transient at the output of the voltage regulator by concurrently activating a plurality of current pull-down switches during the transient and sequentially deactivating each current pull-down switch of the plurality of current pull-down switches after its predetermined deactivation delay for each current pull-down switch.
摘要翻译：一个电路包括一个比较器，用于在电压调节器的输出处监测相对于预定阈值的瞬变，并且如果瞬变超过预定阈值则产生补偿信号。动态电流下拉块从比较器的补偿信号触发，并与电压调节器的输出级一起工作，以通过在期间同时激活多个电流下拉开关来减轻电压调节器输出端的瞬变在每个电流下拉开关的预定去激活延迟之后，暂时并且顺序地去激活多个电流下拉开关中的每个电流下拉开关。

64. 发明授权

US09086887B2 Virtual register mode by designation of dedicated register as destination operand with switch connecting execution result feedback path and turning clock off to register file 有权
标题翻译：通过将专用寄存器指定为目标操作数，通过连接执行结果反馈路径和关闭时钟关闭到寄存器文件的虚拟寄存器模式
公开(公告)号：US09086887B2
公开(公告)日：2015-07-21
申请号：US13228978
申请日：2011-09-09
申请人： Marko Krüger , Steven Bartling , Markus Kösler
发明人： Marko Krüger , Steven Bartling , Markus Kösler
IPC分类号： G06F9/38 , G06F1/32 , G06F9/30
CPC分类号： G06F9/3826 , G06F1/3237 , G06F9/30101 , G06F9/3016 , G06F9/30189 , G06F9/3861
摘要： The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.
摘要翻译：本发明涉及一种用于数据处理的电子设备，其包括具有临时寄存器的执行单元，寄存器文件，从执行单元的数据输出到寄存器文件的第一反馈路径，数据输出的第二反馈路径执行单元发送到临时寄存器，被配置为连接第一反馈路径和/或第二反馈路径的开关以及耦合以控制开关的逻辑级。如果在执行单元的后续操作中使用执行单元的数据输出作为操作数，则控制级被配置为控制开关连接第二反馈路径。

65. 发明申请

US20130082676A1 Fast-settling precision voltage follower circuit and method 有权
公开(公告)号：US20130082676A1
公开(公告)日：2013-04-04
申请号：US13200845
申请日：2011-10-03
申请人： Vadim V. Ivanov , Harish Venkataraman , Susan A. Curtis
发明人： Vadim V. Ivanov , Harish Venkataraman , Susan A. Curtis
IPC分类号： G05F3/02 , H03F1/22
CPC分类号： H03F3/3022 , H03F3/45192 , H03F3/505 , H03F2203/30015
摘要： A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

66. 发明授权

US08384395B2 Circuit for controlling temperature and enabling testing of a semiconductor chip 有权
标题翻译：用于控制温度的电路，并能够测试半导体芯片
公开(公告)号：US08384395B2
公开(公告)日：2013-02-26
申请号：US12774730
申请日：2010-05-06
申请人： Ravindra Karnad , Sudheer Prasad , Ram A Jonnavithula
发明人： Ravindra Karnad , Sudheer Prasad , Ram A Jonnavithula
IPC分类号： H01H31/02
CPC分类号： G01R31/2875 , G01R31/2856
摘要： A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.
摘要翻译：用于控制半导体芯片的温度的电路包括内置在半导体芯片中的第一加热元件。第一加热元件产生热量以增加半导体芯片的温度。芯片还包括耦合到第一加热元件并内置于半导体芯片中的温度控制器。温度控制器控制温度以使半导体芯片能够在期望的温度下进行测试。

67. 发明授权

US07930121B2 Method and apparatus for synchronizing time stamps 有权
标题翻译：用于同步时间戳的方法和装置
公开(公告)号：US07930121B2
公开(公告)日：2011-04-19
申请号：US12195656
申请日：2008-08-21
申请人： Steven Graham Brantley , James Richard MacLean , Francesco Cavaliere
发明人： Steven Graham Brantley , James Richard MacLean , Francesco Cavaliere
IPC分类号： G01R29/02
CPC分类号： H03L7/0812 , G04F10/04 , G04F10/06 , H03L7/10
摘要： Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally limited by clock speed. Here, an apparatus is provided that performs time stamp operations and is not generally limited by clock speed. This apparatus generally uses an interpolator, counter, lathing circuits, and a synchronizer. Typically, the interpolator provides a residue signal to the synchronizer, and the synchronizer can determines whether to add the interpolation signal to a counter state based at least in part on a comparison of an event signal and the residue signal.
摘要翻译：传统上，时间标记电路已被用于精确的数字时间测量。然而，这些类型的电路的分辨率通常受时钟速度的限制。这里，提供了一种执行时间戳操作并且通常不受时钟速度限制的装置。该装置通常使用内插器，计数器，车床电路和同步器。通常，内插器向同步器提供残留信号，并且同步器可以至少部分地基于事件信号和残差信号的比较来确定是否将内插信号添加到计数器状态。

68. 发明申请

US20110085631A1 METHOD AND APPARATUS FOR UNIT INTERVAL CALCULATION 有权
标题翻译：用于单位间隔计算的方法和装置
公开(公告)号：US20110085631A1
公开(公告)日：2011-04-14
申请号：US12970408
申请日：2010-12-16
申请人： Gary F. Chard , T-Pinn R. Koh
发明人： Gary F. Chard , T-Pinn R. Koh
IPC分类号： H04L7/02
CPC分类号： H04L25/4904
摘要： A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.
摘要翻译：提供了一种方法。在该方法中，接收时钟信号和输入信号，其中输入信号是曼彻斯特编码信号。对于接收到有效UI的每个UI，单位间隔（UI）号码增加。在UI号码的每个增量之后，将UI号码与多个阈值进行比较，其中每个阈值与多个和值中的至少一个相关联。对于每个阈值，一旦超过UI号码，其和值对于时钟信号的每个周期递增，并且计算多个窗口长度，其中每个窗口至少部分地基于以下各项中的至少一个来计算： UI值的预定值的和值。

69. 发明申请

US20100193944A1 Semiconductor Flip-Chip System Having Oblong Connectors and Reduced Trace Pitches 有权
标题翻译：半导体倒装芯片系统具有连续的连接器和减少的跟踪间距
公开(公告)号：US20100193944A1
公开(公告)日：2010-08-05
申请号：US12503553
申请日：2009-07-15
申请人： Abram M. CASTRO , Mark A. GERBER
发明人： Abram M. CASTRO , Mark A. GERBER
IPC分类号： H01L23/498
CPC分类号： H01L24/13 , H01L23/49811 , H01L24/06 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05147 , H01L2224/0558 , H01L2224/05638 , H01L2224/05655 , H01L2224/13005 , H01L2224/13012 , H01L2224/13147 , H01L2224/16238 , H01L2924/00013 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/13099
摘要： A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length (111) and a first width (112), the first width being uniform along the first length, and further a pitch (114) to respective adjacent traces. The semiconductor chip has a second surface (102a) including contact pads (121); the second surface faces the first surface spaced apart by a gap (130). A conductive pillar (140) contacts each contact pad; the pillar includes a metal core (141) and a solder body (142), which connects the core to the respective trace across the gap. The pillar core (141) has an oblong cross section of a second width (151) and a second length (152) greater than the second width. Trace pitch (141) is equal to or smaller than twice the second width (151). The trace pitch is equal to or smaller than the second length (152).
摘要翻译：组装在基板（101）上的半导体芯片（102）。衬底具有包括具有第一长度（111）和第一宽度（112）的导电迹线（110）的第一表面（101a），第一宽度沿着第一长度是均匀的，并且还有一个间距（114）到相应的相邻轨迹。半导体芯片具有包括接触焊盘（121）的第二表面（102a）; 所述第二表面面向所述第一表面，间隔开间隙（130）。导电柱（140）接触每个接触垫; 支柱包括金属芯（141）和焊料体（142），其将芯连接到穿过间隙的相应迹线。柱芯（141）具有第二宽度（151）的长方形横截面和大于第二宽度的第二长度（152）。痕迹间距（141）等于或小于第二宽度（151）的两倍。迹线间距等于或小于第二长度（152）。

70. 发明申请

US20100073397A1 System and Method for Grouped Pixel Addressing 有权
标题翻译：用于分组像素寻址的系统和方法
公开(公告)号：US20100073397A1
公开(公告)日：2010-03-25
申请号：US12236379
申请日：2008-09-23
申请人： Andrew G. Huibers , Michael T. Davis , Henry W. Neal , James N. Hall
发明人： Andrew G. Huibers , Michael T. Davis , Henry W. Neal , James N. Hall
IPC分类号： G09G5/02
CPC分类号： G09G3/346 , G09G3/2022 , G09G2300/0439 , G09G2310/0235
摘要： In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes receiving a data stream representing a frame of an image. The data stream may indicate a first color pixel cluster corresponding to a first color and a second color pixel cluster corresponding to a second color. The first color pixel cluster and the second color pixel cluster may be displayed. The first color pixel cluster may be different from the second color pixel cluster.
摘要翻译：根据本公开的教导，提供了一种用于显示图像的系统和方法。在一个实施例中，该方法包括接收表示图像帧的数据流。数据流可以指示对应于第一颜色的第一颜色像素簇和对应于第二颜色的第二颜色像素簇。可以显示第一颜色像素簇和第二颜色像素簇。第一颜色像素簇可以不同于第二颜色像素簇。

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