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61. 发明公开

EP1271782A3 FPGA with at least two different and independently configurable memory structures 有权
标题翻译： FPGA具有至少两个不同的且独立配置的存储器结构
公开(公告)号：EP1271782A3
公开(公告)日：2003-07-23
申请号：EP02012610.8
申请日：2002-06-06
申请人： STMicroelectronics Pvt. Ltd
发明人： Singh, Moninder , Chaudhry, Anurag
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field programmable logic device comprising at least two independently configurable embedded memory structures wherein said memory structures differ in at least one of the following parameter memory size available configuration depths available configuration widths for efficient memory utilization.

62. 发明公开

EP1320048A2 Rapid partial configuration of reconfigurable devices 审中-公开
标题翻译： Schnelle Teilkonfiguration von rekonfigurierbaren Vorrichtungen
公开(公告)号：EP1320048A2
公开(公告)日：2003-06-18
申请号：EP02027923.8
申请日：2002-12-13
申请人： STMicroelectronics Pvt. Ltd
发明人： Goel, AshishKumar , Agarwal, Manish
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A system and method for enabling rapid partial configuration of reconfigurable devices, wherein configuration definition means define partial configuration requirements, and contain at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. Configuration loading means (300, 310, 320) provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements.
摘要翻译：一种用于实现可重配置设备的快速部分配置的系统和方法，其中配置定义装置定义部分配置要求，并且至少包含用于部分重配置的配置数据的起始地址，指定要重新配置的连续位置的数量的数据大小，以及对应于相邻位置的期望的配置数据。配置加载装置（300,310,320）根据部分配置要求提供将配置数据加载到可重配置设备中。

63. 发明授权

EP2348634B1 Low consumption flip-flop circuit with data retention and method thereof 有权转让
标题翻译：触发器电路具有低功耗和与数据存储及其方法
公开(公告)号：EP2348634B1
公开(公告)日：2014-03-19
申请号：EP10197058.0
申请日：2010-12-27
申请人： STMicroelectronics Srl , STMicroelectronics Pvt. Ltd.
发明人： Veggetti, Andrea Mario , Jain, Abhishek , Rohilla, Pankaj
IPC分类号： H03K3/037 , H03K3/356 , H03K19/00
CPC分类号： H03K3/012 , H03K3/0375 , H03K3/356008 , H03K19/0016

64. 发明公开

EP2385484A1 Object detection in an image 审中-公开
标题翻译：在einem Bild的Objektdetektion
公开(公告)号：EP2385484A1
公开(公告)日：2011-11-09
申请号：EP10305478.9
申请日：2010-05-06
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics Pvt. Ltd
发明人： Chotard, Ludovic , Sanches, Michel , Schwambach, Vitor , Chandra, Mahesh
IPC分类号： G06K9/00
CPC分类号： G06K9/00228 , G06K9/6257
摘要： The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions (310, 312, 314) of a first search window (108); generating a cumulative score based on results of said one or more tests on said plurality of sub-regions; comparing said cumulative score with a threshold value; and based on said comparison, selectively performing one or more tests of said test sequence on at least one further sub-region of said first search window, said at least one further sub-region at least partially overlapping each of said plurality of sub-regions.
摘要翻译：本发明涉及一种通过图像处理装置执行图像中的对象检测的方法，包括：对多个至少部分重叠的子区域的像素值执行用于检测第一对象的测试序列的一个或多个测试（108,312）的第一搜索窗口（310,312,314）; 基于对所述多个子区域的所述一个或多个测试的结果生成累积分数; 将所述累积分数与阈值进行比较; 并且基于所述比较，在所述第一搜索窗口的至少一个另外的子区域上选择性地执行所述测试序列的一个或多个测试，所述至少一个另外的子区域至少部分地与所述多个子区域中的每一个子区域重叠。

65. 发明公开

EP1677175A3 Dynamic power management in system on chips (SOC) 有权转让
标题翻译：对于系统级芯片（SOC）动态电源管理
公开(公告)号：EP1677175A3
公开(公告)日：2011-05-04
申请号：EP05113079.7
申请日：2005-12-29
申请人： STMicroelectronics Pvt. Ltd.
发明人： Uguen, Laurent , Dhiman, Gaurav , Kapoor, Gaurav
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low power state based on said feasibility, a means for decreasing the power centric communication between various processors and a means for increasing the low power mode time. Thus a framework is proposed in the instant invention wherein all the device drivers dynamically maintain the information on the feasibility of a low power transition at any point of time. Thus whenever an opportunity to enter a low power mode comes up one has to just check this feasibility variable to determine whether the low power mode entry is viable or not. For ensuring the safe transition to a low power mode, a stalling machine is proposed in case of DSPs. For further saving power, a power centric communication channel is established between various processors and to reduce the load on this communication channel techniques like quad-ring buffer and DSP feedback are proposed.

66. 发明公开

EP1653747A3 A system for clock recovery in digital video communication 有权
标题翻译：设备在数字视频通信时钟恢复
公开(公告)号：EP1653747A3
公开(公告)日：2009-06-17
申请号：EP05022773.5
申请日：2005-10-19
申请人： STMicroelectronics Pvt. Ltd
发明人： Kaushik, Saha , Chakraborty, Chiranjib , Chatterjee, Subrata
IPC分类号： H04N7/62
CPC分类号： H04N21/4305
摘要： A system for clock recovery in digital video communication comprising a delay measurement block for generating PCR input signals and for continuously determining time interval between successive PCR input signals, a first storage device for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals, a PCR inter-arrival time computation filtering device for determining the average time of arrival difference between successive PCR packets. An error correction device for minimizing the error in the average PCR difference between successive PCR packets, a controlled system clock generator connected to the output of said error correction device to generate system clock, a second storage device for generating a first system clock output, a controlled clock period difference computation element for computing the clock period difference between said first and second system clock output, and said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.

67. 发明公开

EP1672791A3 A glitch free controlled ring oscillator 审中-公开
标题翻译：失败的自由干控制环形振荡器
公开(公告)号：EP1672791A3
公开(公告)日：2008-09-17
申请号：EP05112285.1
申请日：2005-12-16
申请人： STMicroelectronics Pvt. Ltd
发明人： Tiwari, Naveen , Singh, Balwant
IPC分类号： H03K3/03
CPC分类号： G06F1/04 , H03K3/0315 , H03K3/70
摘要： A glitch free controlled ring oscillator comprising a programmable delay chain (1) connected to a gating and inverting means (3) wherein a latching means (2) is provided between said prgrammable delay chain (1) and said gating and inverting means (3) for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

68. 发明公开

EP1742229A3 A built-in self-repairable memory 审中-公开
标题翻译：内置selbstreparierbarer内存
公开(公告)号：EP1742229A3
公开(公告)日：2008-05-21
申请号：EP06115639.4
申请日：2006-06-19
申请人： STMicroelectronics Pvt. Ltd
发明人： Dubey, Prashant , Kashyap, Amit
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , G11C29/4401 , G11C29/812
摘要： The present invention provides a built-in self-repairable memory. The invention repairs the faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses lesser number of fuses to actually make a perfect repair and thus result into a yield enhancement. The fuse data is stored in a compressed form and then decompressed at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).

69. 发明公开

EP1727156A3 An improved area efficient memory architecture with decoder self test and debug capability 有权转让
标题翻译：改进的范围内高效的内存架构解码器自动测试和调试能力
公开(公告)号：EP1727156A3
公开(公告)日：2008-04-09
申请号：EP06114150.3
申请日：2006-05-18
申请人： STMicroelectronics Pvt. Ltd.
发明人： DUBEY, Prashant
IPC分类号： G11C29/02
CPC分类号： G11C29/02 , G11C5/025 , G11C29/024 , G11C2029/1206
摘要： The invention provides an integrated test device thereby reducing external wiring congestion to the memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

70. 发明公开

EP1901430A2 High speed level shifter 有权
标题翻译：高速电平转换器
公开(公告)号：EP1901430A2
公开(公告)日：2008-03-19
申请号：EP07114839.9
申请日：2007-08-23
申请人： STMicroelectronics Pvt. Ltd.
发明人： Srivastava, Ankit , Jandial, Sourav
IPC分类号： H03K19/0185
CPC分类号： H03K19/018528 , H03K3/012 , H03K3/356165 , H03K3/356182
摘要： The present invention provides a level shifter circuit capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuit, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operations.
摘要翻译：本发明提供了一种能够进行高频操作的电平移位器电路。当输入信号从高逻辑电平切换到低逻辑电平时，电平移位器电路利用动态电荷注入器件，其减小输入NMOS器件的栅极和漏极之间的电容耦合效应。动态电荷注入器件集成在输出节点上，为电平转换器电路提供初始推力，触发交叉耦合上拉PMOS器件的正向再生反馈，从而实现快速转换，从而实现高频操作。

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