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51. 实用新型

JPS5986097U JPS5986097U - 失效
公开(公告)号：JPS5986097U
公开(公告)日：1984-06-11
申请号：JP13375883
申请日：1983-08-31
IPC分类号： G11C11/41 , G11C11/4091 , G11C11/4096 , G11C11/419 , H03K3/356 , G11C11/34 , G11C7/06
CPC分类号： G11C11/4091 , G11C11/4096 , G11C11/419 , H03K3/356043

52. 发明专利

JP5759693B2 I/Q不整合を補償する発振信号発生器及びそれを含む通信システム有权
标题翻译： I / Q振荡器信号发生器，并且包括相同的，以补偿失配的通信系统
公开(公告)号：JP5759693B2
公开(公告)日：2015-08-05
申请号：JP2010206739
申请日：2010-09-15
申请人：三星電子株式会社 , Samsung Electronics Co.,Ltd.
发明人：張宰洪
IPC分类号： H04B1/30 , H04B1/40 , H04L27/34
CPC分类号： H03K5/15006 , H03B27/00 , H03K3/356043 , H04B1/0475 , H04B1/30

53. 发明专利

JP2009130457A Semiconductor integrated circuit and electronic circuit 有权
标题翻译：半导体集成电路和电子电路
公开(公告)号：JP2009130457A
公开(公告)日：2009-06-11
申请号：JP2007300834
申请日：2007-11-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YAMAMOTO TAKUJI
IPC分类号： H03K3/3562 , H01L21/822 , H01L27/04 , H03K3/45
CPC分类号： H03K3/356043
摘要： PROBLEM TO BE SOLVED: To provide a latch circuit and a flip flop circuit which can be stably operated at a high speed with a low power voltage. SOLUTION: The semiconductor integrated circuit includes: a first differential circuit for transmitting input data to a prescribed node in response to a first signal level of a clock signal; a second differential circuit for holding data of the prescribed node at a fixed value in response to a second signal level of the clock signal; a clock transmission circuit to which a current corresponding to the clock signal flows; and a transformer circuit for coupling the first differential circuit, the second differential circuit, and the clock transmission circuit. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在低功率电压下以高速稳定运行的锁存电路和触发电路。解决方案：半导体集成电路包括：第一差分电路，用于响应于时钟信号的第一信号电平将输入数据发送到规定的节点; 第二差分电路，用于响应于时钟信号的第二信号电平将规定节点的数据保持在固定值; 与时钟信号对应的电流流过的时钟传输电路; 以及用于耦合第一差分电路，第二差分电路和时钟传输电路的变压器电路。版权所有（C）2009，JPO＆INPIT

54. 发明专利

JP2005318608A Differential current mode phase/frequency detector circuit 审中-公开
公开(公告)号：JP2005318608A
公开(公告)日：2005-11-10
申请号：JP2005129076
申请日：2005-04-27
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： MELTZER DAVID , PADAPARAMBIL MURALIKUMAR A , TAT C WU
IPC分类号： H03K3/3562 , H03D13/00 , H03K3/356 , H03K19/094 , H03K19/096 , H03K19/20 , H03L7/085 , H03L7/089
CPC分类号： H03K3/356043 , H03D13/00 , H03L7/085
摘要： PROBLEM TO BE SOLVED: To provide a phase and frequency detector having a differential architecture so that its operation can be performed at the highest possible frequency and with low noise generation. SOLUTION: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and responds to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration. COPYRIGHT: (C)2006,JPO&NCIPI

55. 发明专利

JPS61120518A Clocked comparator 失效
标题翻译：时钟比较器
公开(公告)号：JPS61120518A
公开(公告)日：1986-06-07
申请号：JP24909485
申请日：1985-11-08
申请人： Philips Nv
发明人： MISHIERU JIYOSEFU MARII BINE , TEIARII DOUKURAN
IPC分类号： H03K5/08 , H03K3/356 , H03K3/3562
CPC分类号： H03K3/356043 , H03K3/3562

56. 发明公开

EP3018828A1 PHASE DETECTOR 有权
标题翻译： PHASENDETEKTOR
公开(公告)号：EP3018828A1
公开(公告)日：2016-05-11
申请号：EP15175185.6
申请日：2015-07-03
申请人： MediaTek, Inc
发明人： Chen, Pang-Ning , Hsueh, Yu-Li , Wu, Pi-An
IPC分类号： H03L7/085
CPC分类号： H03L7/089 , H03K3/356043 , H03K5/1565 , H03L7/085
摘要： A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.
摘要翻译：提供一种包括第一锁存器和控制电路的相位检测器。第一锁存器响应于第一输入信号和第二输入信号之间的相位差产生第一输出信号和第二输出信号。第一和第二输出信号中的每一个包括相位差的第一相位信息和第二相位信息。控制电路根据相位差的第一相位信息产生相位指示信号。相位指示信号表示第一输入信号和第二输入信号之间的相对位置。

57. 发明公开

EP1714388A1 LATCH CIRCUIT 审中-公开
标题翻译：锁存电路
公开(公告)号：EP1714388A1
公开(公告)日：2006-10-25
申请号：EP05702773.2
申请日：2005-01-25
申请人： Koninklijke Philips Electronics N.V.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , CISSE, Idrissa
IPC分类号： H03K19/086
CPC分类号： H03K3/356043
摘要： A latch circuit (1) comprising, a differential input with an inverting input (D+) and a non-inverting input (D-). The latch further comprises a differential output with an inverting output (Q+) and a non-inverting output (Q-). One of the outputs (Q-) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output s in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold, respectively.

58. 发明公开

EP1488517A1 PROGRAMMABLE DIFFERENTIAL D FLIP-FLOP 有权
标题翻译：可编程差动D-FLOP
公开(公告)号：EP1488517A1
公开(公告)日：2004-12-22
申请号：EP03744155.7
申请日：2003-03-04
申请人： TERADYNE, INC.
发明人： LING, Kuok
IPC分类号： H03K3/289 , H03K19/094
CPC分类号： H03K3/3562 , H03K3/356043
摘要： A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay of the flip-flop.

59. 发明公开

EP1420512A1 Phase detector with delay elements for improved data regeneration 有权
标题翻译： Phasendetektor mitVerzögerungselementenfürverbesserte Datenregeneration
公开(公告)号：EP1420512A1
公开(公告)日：2004-05-19
申请号：EP03026076.4
申请日：2003-11-12
申请人： Broadcom Corporation
发明人： Cao, Jun , Momtaz, Afshin
IPC分类号： H03D13/00 , G01R25/04
CPC分类号： H03L7/085 , H03D13/003 , H03K3/356043 , H03K3/3562 , H03L7/087 , H03L7/091 , H03L7/113 , H03L7/14 , H04L7/033
摘要： Circuits and methods for simplifying clock and data recovery circuits by including a data regeneration circuit as part of a phase detector circuit. Delay elements are added such that the timing of the data recovery is optimized or improved with little or no effect on the clock recovery operation. This allows die area and power supply savings, while retaining the ability to adjust data recovery timing.
摘要翻译：通过包括作为相位检测器电路的一部分的数据再生电路来简化时钟和数据恢复电路的电路和方法。添加延迟元素，使得数据恢复的时序被优化或改进，对时钟恢复操作几乎没有影响或没有影响。这样可以节省模具面积和电源，同时保留调整数据恢复时间的能力。

60. 发明授权

EP0774836B1 Latch circuit for receiving small amplitude signals 失效
标题翻译：锁存电路，用于接收的低幅度信号
公开(公告)号：EP0774836B1
公开(公告)日：2004-01-28
申请号：EP96118278.9
申请日：1996-11-14
申请人： NEC Electronics Corporation
发明人： Takahashi, Hiroyuki
IPC分类号： H03K3/356 , H03K19/0175
CPC分类号： H03K3/356069 , H03K3/021 , H03K3/356043

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