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51. 发明公开

EP0078725A2 Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure 失效
标题翻译：一种用于制备亚微米双极晶体管不外延生长和所得到的结构的过程。
公开(公告)号：EP0078725A2
公开(公告)日：1983-05-11
申请号：EP82401917.8
申请日：1982-10-19
申请人： FAIRCHILD SEMICONDUCTOR CORPORATION
发明人： Ko, Wen-Chuang
IPC分类号： H01L21/76 , H01L29/72
CPC分类号： H01L29/7325 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.4 microns, thereby substantially reducing the lateral oxidation of the semiconductor silicon islands and making possible devices of extremely small size, typically around 16-18 square microns. During the implantation of channel stop regions between the islands of semiconductor material a thin oxide layer is used to screen the underlying silicon from forming oxidation-induced stacking faults by the subsequent high dose field implantation and oxidation. A nitrogen anneal following this implantation and prior to forming the field oxide further reduces the frequency of stacking faults.
摘要翻译：垂直双极晶体管被制造在一半导体基片，而无需使用隔离和离子注入技术的氧化外延层。在KEV范围离子植入能量来植入选择离子进入衬底，以形成集电极区域和埋入集电极层从所述装置的表面小于1微米，并tlien到forrn相反导电型的基极区中的集电层和在所述基极区的第一导电类型的发射极区。即使离子注入技术是，用于形成所有区域，基助剂的发射极区，如果需要清除，FORMED是邻接用于后期反弹场氧化物限定半导体材料的岛。场氧化物被形成为小于1微米，厚度通常在appioxiniately 0.4微的从而大大减少横向氧化等粘结半导体硅岛和制造非常小尺寸的可能的设备，典型地为约16-18平方微米的thicknes。在半导体材料的岛之间沟道停止区域的注入的薄氧化物层被用来筛选从形成通过随后的高剂量植入字段和氧化的氧化引起的堆垛层错的底层硅。甲氮退火在此之后注入和形成场氧化物之前进一步降低堆垛层错的频率。

52. 发明公开

EP0058604A1 Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions 失效
标题翻译：一种制造半导体结构的方法，具有减少的埋入区之间的横向间距。
公开(公告)号：EP0058604A1
公开(公告)日：1982-08-25
申请号：EP82400231.5
申请日：1982-02-09
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Caldwell, Robert E.
IPC分类号： H01L21/76
CPC分类号： H01L21/76216 , H01L21/26513 , H01L21/74 , H01L21/7621
摘要： The lateral spacing between buried regions separated by oxide-isolation regions in a semiconductor structure is reduced to as little as one micron by performing a deep implantation of ions of the conductivity type opposite to that of the buried regions generally into portions of the substrate below the sites where the oxide-isolation regions are formed.

53. 发明授权

EP0731983B1 IMPROVED ISOLATION BETWEEN DIFFUSION LINES IN A MEMORY ARRAY 失效
标题翻译： BETWEEN DIFFUSIONS LINES改进的绝缘在存储领域
公开(公告)号：EP0731983B1
公开(公告)日：2002-11-27
申请号：EP95931812.2
申请日：1995-09-13
申请人： INTEL CORPORATION
发明人： ONG, Tong-Chern , TANG, Daniel, N.
IPC分类号： H01L21/8246 , H01L21/8247 , H01L21/762
CPC分类号： H01L21/7621 , H01L21/76216 , H01L21/76221 , H01L27/105 , H01L27/11521
摘要： A method of forming a memory device with improved isolation between diffusion lines. Parallel, spaced apart thick oxide strips (201) are grown on a substrate. Next, spaced apart, parallel strips (302) having a polysilicon (302a) and nitride (302b) layer, oriented perpendicular to the first strips (201), are formed. The oxide (201) between the second strips is removed, followed by an implantation to form source (402) and drain (401) regions. The nitride layer (302b) on the second strips is removed on those strips between two drain diffusions (401) and an oxidation is performed to form self-aligned thick oxide (602) over the source and drain regions. The strips from which the nitride has been removed are also oxidized, thus providing isolation between adjacent drain lines.

54. 发明授权

EP0080731B2 Semiconductor device comprising a buried oxide isolation 失效
标题翻译：包含氧化银分离的半导体器件
公开(公告)号：EP0080731B2
公开(公告)日：1991-11-21
申请号：EP82111034.3
申请日：1982-11-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Konaka, Masami , Shibyo, Naoyuki , Dang, Ryo
IPC分类号： H01L29/78 , H01L21/76 , H01L29/08
CPC分类号： H01L21/7621 , H01L21/76 , H01L21/76216 , H01L29/0847
摘要： A semiconductor device comprising a semiconductor substrate (10) having a transistor region (20) in which a field-effect transistor having a channel width of 1 mu or less is formed, and an insulating film (12) deposited in recesses formed in the part of the semiconductor substrate surrounding the transistor region. The angle theta that is formed between the side wall (22) of the recesses and the imaginary extension of the top surface (24) of the transistor region is defined as: theta + 0.2778 epsilon 1 - 1.639 epsilon 1 + 88.39 theta >/= - 0.009259 epsilon 1 - 0.2222 epsilon 1 - 2.528 epsilon 1 + 76.76 theta >/= 50 DEG and epsilon 1 >/= 1, where epsilon 1 is the relative permittivity of the insulating film.

55. 发明公开

EP0326549A1 A LOCAL OXIDATION OF SILICON PROCESS 失效
标题翻译：法国产化使硅氧化。
公开(公告)号：EP0326549A1
公开(公告)日：1989-08-09
申请号：EP87905246.0
申请日：1987-08-17
申请人： PLESSEY OVERSEAS LIMITED
发明人： DUNCAN, Shane
IPC分类号： H01L21
CPC分类号： H01L21/7621
摘要： A LOCOS process, a process of the type wherein a capped recessed mesa structure (1, 3) is defined in single crystal, semiconductor grade, silicon and thereafter, and in the presence of the capping layers (5, 7), local oxide (13) is thermally grown to provide an isolation structure. This process is modified by introducing a layer (11) of passive oxide deposit to cover the substrate (3), mesa (1) and upper capping layer (7) prior to the thermal growth of further oxide (13). The resulting oxide (13) is then etched back to remove excess material. This modification results in reduced bird's head height non-plan arity and also in reduced bird's beak encroachment into the active area of the silicon device (3). Re-entrancy at the base of the bird's head (13) is also eliminated.

56. 发明授权

EP0134166B1 Wafer fabrication by implanting through protective layer 失效
标题翻译：通过保护层进行加工制造
公开(公告)号：EP0134166B1
公开(公告)日：1988-03-16
申请号：EP84401427.4
申请日：1984-07-05
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Howell, Paul J. , Currier, Gregory B.
IPC分类号： H01L21/265 , H01L21/82
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/2652 , H01L21/3145 , H01L21/7621 , H01L21/76216 , H01L21/8222

57. 发明公开

EP0215218A3 A method of forming recessed oxide isolation with reduced steepness of the birds' neck 失效
标题翻译：形成氧化铁分离的方法，具有降低胆固醇的耐受性
公开(公告)号：EP0215218A3
公开(公告)日：1987-08-26
申请号：EP86109127
申请日：1986-07-04
申请人： International Business Machines Corporation
发明人： Christie, Rosemary , Hwang, Bao-Tai , Ku, San-Mei , Sickler, Janet Marion
IPC分类号： H01L21/76
CPC分类号： H01L21/7621 , H01L21/3081
摘要： Disclosed is a method of forming in a monocrystalline silicon body an optimum recessed oxide isolation structure with reduced steepness of the bird's neck. Starting from a monocrystalline silicon body (20,21), there is formed thereon a layered structure of first silicon dioxide (22), polycrystalline silicon (23), second silicon dioxide (24) and silicon nitride (25), in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form the oxide isolation pattern within the silicon body. The exposed areas of the silicon body are anisotropically reactive ion etched to an initial portion (27) of the desired depth obtaining the corresponding portion of the trench (30) having substantially vertical walls. Then by chemical etching the trench is extended to a final portion (28) of the desired depth obtaining inwardly sloped walls in the final portion. The body is then thermally oxidized until the desired oxide isolation penetrates to the desired depth within the silicon body.

58. 发明公开

EP0084465A3 Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM 失效
标题翻译：标准RAM / PROM和侧向PNP单元RAM的氧化物隔离过程
公开(公告)号：EP0084465A3
公开(公告)日：1986-02-05
申请号：EP83400012
申请日：1983-01-04
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Shideler, Jay Albert , Mishra, Umeshwar Dutt
IPC分类号： H01L21/76 , H01L27/06 , H01L27/08 , H01L29/06 , G11C17/00
CPC分类号： H01L21/8224 , H01L21/7621 , H01L27/0233 , H01L27/1026 , H01L29/0615
摘要： An oxide-isolated RAM and PROM process disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by eliminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit construction using the structure of this invention. The process also can be used to manufacture PROMS from vertical NPN transistors. An LV CEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allowing junction avalanching of selected emitter base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.

59. 发明公开

EP0098775A2 Procédé de réalisation de l'oxyde de champ d'un circuit intégré 失效
标题翻译：一种用于实现一个场氧化物的用于集成电路的过程。
公开(公告)号：EP0098775A2
公开(公告)日：1984-01-18
申请号：EP83401332.8
申请日：1983-06-28
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： Jeuch, Pierre , Parrens, Pierre
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/76216 , H01L21/31055 , H01L21/76205 , H01L21/7621 , Y10S438/978
摘要： L'invention concerne un procédé de réalisation de l'oxyde de champ d'un circuit intégré.
Ce procédé comprend les étapes successives suivantes: réalisation d'une gravure anisotrope, sur une hauteur h, d'une région (20b) d'un substrat (20) semiconducteur dopé, dans laquelle on va réaliser l'oxyde de champ; implantation d'ions dans ladite région (20b) du substrat restante, donnant un dopage du même type que celui du substrat; dépôt d'une couche d'oxyde (32) sur l'ensemble du substrat; dépôt d'une couche de résine (34) sur la couche d'oxyde, et réalisation d'une gravure simultanée de la couche de résine et de la couche d'oxyde jusqu'à élimination totale de la région (32a) de la couche d'oxyde, située au-dessus d'une autre région (20a) du substrat dans laquelle sera réalisé le composant actif du circuit intégré.

60. 发明公开

EP0080731A2 Semiconductor device comprising a buried oxide isolation 失效
标题翻译： Halbleiteranordnung mit einer vergrabenen Isolation aus Oxyd。
公开(公告)号：EP0080731A2
公开(公告)日：1983-06-08
申请号：EP82111034.3
申请日：1982-11-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Konaka, Masami , Shibyo, Naoyuki , Dang, Ryo
IPC分类号： H01L29/78 , H01L21/76 , H01L29/08
CPC分类号： H01L21/7621 , H01L21/76 , H01L21/76216 , H01L29/0847
摘要： A semiconductor device comprising a semiconductor substrate (10) having a transistor region (20) in which a field-effect transistor having a channel width of 1 µ or less is formed, and an insulating film (12) deposited in recesses formed in the part of the semiconductor substrate surrounding the transistor region. The angle 8 that is formed between the side wall (22) of the recesses and the imaginary extension of the top surface (24) of the transistor region is defined as: and ε 1 ≥ 1, where ε 1 is the relative permittivity of the insulating film.
摘要翻译：一种半导体器件，包括具有其中形成沟道宽度为1μm以下的场效应晶体管的晶体管区域（20）的半导体衬底（10），以及沉积在形成在所述部分中的凹部中的绝缘膜（12）围绕晶体管区域的半导体衬底。在凹部的侧壁（22）和晶体管区域的顶表面（24）的虚拟延伸部之间形成的角度θ被定义为：θ=0.02778ε1 2 +0.2778ε1 2 = 1.639ε1 + 88.39°θ/ = - 0.009259ε1 3 - 0.2222ε1 -2 2.528ε1 + 76.76°θ= 50°，ε1> = 1，其中ε1 是绝缘膜的相对介电常数。

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