专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明公开

EP0395240A3 High speed numerical processor 失效
标题翻译：高速数字处理器
公开(公告)号：EP0395240A3
公开(公告)日：1992-08-12
申请号：EP90303654.9
申请日：1990-04-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Steiss, Donald E. , Hipona, Maria B. , Darley, Henry M.
IPC分类号： G06F7/52 , G06F7/552 , G06F7/48
CPC分类号： G06F7/5324 , G06F7/535 , G06F7/5525 , G06F7/57 , G06F2207/382 , G06F2207/5355
摘要： Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48)(50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

52. 发明授权

KR101411683B1 감소된 면적을 갖는 승법식 제산 회로 有权
标题翻译：具有减少面积的多路分段电路
公开(公告)号：KR101411683B1
公开(公告)日：2014-06-25
申请号：KR1020127000695
申请日：2010-06-10
申请人： 시놉시스, 인크.
发明人： 한경남 , 텐카알렉산드르 , 트랜데이비드 , 켈리릭
IPC分类号： G06F7/52 , G06F17/50
CPC分类号： G06F7/535 , G06F2207/5355
摘要： 본 기술은 회로 면적이 감소된 제산 회로이다. 실시형태는 피제수 입력과 제수 입력의 승법식 제산을 구현하는 집적 회로를 포함한다. 집적 회로는 룩업 테이블 회로와 곱셈기 회로를 포함한다. 룩업 테이블 회로는 제수 입력의 역수의 근사치를 제공한다. 곱셈기 회로는 피제수 입력과 제수 입력의 몫 출력의 근사치를 수신하고 세분한다. 복수의 곱셈기 회로들 중 적어도 하나는 감소된 수의 중간 부분 곱으로 승산을 구현하는 제곱 회로이다. 감소된 수의 중간 부분 곱은 제곱 회로가 임의의 2개의 동일하지 않은 수를 승산하는 것을 방지하고 제곱 회로가 동일한 수를 동일한 수로 승산하는 것으로 제한한다.

53. 发明公开

KR1020120017468A 감소된 면적을 갖는 승법식 제산 회로 有权
标题翻译：具有减少面积的多路分段电路
公开(公告)号：KR1020120017468A
公开(公告)日：2012-02-28
申请号：KR1020127000695
申请日：2010-06-10
申请人： 시놉시스, 인크.
发明人： 한경남 , 텐카알렉산드르 , 트랜데이비드 , 켈리릭
IPC分类号： G06F7/52 , G06F17/50
CPC分类号： G06F7/535 , G06F2207/5355
摘要： 본 기술은 회로 면적이 감소된 제산 회로이다. 실시형태는 피제수 입력과 제수 입력의 승법식 제산을 구현하는 집적 회로를 포함한다. 집적 회로는 룩업 테이블 회로와 곱셈기 회로를 포함한다. 룩업 테이블 회로는 제수 입력의 역수의 근사치를 제공한다. 곱셈기 회로는 피제수 입력과 제수 입력의 몫 출력의 근사치를 수신하고 세분한다. 복수의 곱셈기 회로들 중 적어도 하나는 감소된 수의 중간 부분 곱으로 승산을 구현하는 제곱 회로이다. 감소된 수의 중간 부분 곱은 제곱 회로가 임의의 2개의 동일하지 않은 수를 승산하는 것을 방지하고 제곱 회로가 동일한 수를 동일한 수로 승산하는 것으로 제한한다.

54. 发明授权

US11782077B2 System and method for performing a line-wise power flow analysis for a power system 有权
公开(公告)号：US11782077B2
公开(公告)日：2023-10-10
申请号：US16233745
申请日：2018-12-27
申请人： Balasubramanian Venkatesh , Amr Adel Fathy Mohamed
发明人： Balasubramanian Venkatesh , Amr Adel Fathy Mohamed
IPC分类号： G01R21/00 , G01R21/133 , G06F7/483 , G06F7/544 , H02J3/06
CPC分类号： G01R21/003 , G01R21/005 , G01R21/1331 , G06F7/483 , G06F7/544 , H02J3/06 , G06F2207/5355
摘要： Various embodiments are provided for conducting a power flow analysis using a set of line-wise power balance equations. In at least some embodiment, the set of line-wise power balance equations is solved using a Newton-Raphson technique. In various cases, the Jacobian matrix generated by the Newton-Raphson technique may directly indicate the transmission lines, or sets of transmission lines, which are most susceptible to voltage collapse. In at least one example application, the set of line-wise power balance equations may be used as equality constraints in an optimal power flow (OPF) formulation for solving an optimal power flow (OPF) problem.

55. 发明申请

US20160041947A1 IMPLEMENTING A SQUARE ROOT OPERATION IN A COMPUTER SYSTEM 有权
标题翻译：在计算机系统中实现方圆操作
公开(公告)号：US20160041947A1
公开(公告)日：2016-02-11
申请号：US14452358
申请日：2014-08-05
申请人： Imagination Technologies, Limited
发明人： Leonard Rarick
IPC分类号： G06F17/10
CPC分类号： G06F7/5525 , G06F2207/5355
摘要： A method and computer system are provided for implementing a square root operation using an iterative converging approximation technique. The method includes fewer computations than conventional methods, and only includes computations which are simple to implement in hardware on a computer system, such as multiplication, addition, subtraction and shifting. Therefore, the methods described herein are adapted specifically for being performed on a computer system, e.g. in hardware, and allow the computer system to perform a square root operation with low latency and with low power consumption.
摘要翻译：提供了一种使用迭代收敛逼近技术实现平方根操作的方法和计算机系统。该方法包括比常规方法更少的计算，并且仅包括在计算机系统上的硬件中简单实现的计算，例如乘法，加法，减法和移位。因此，本文描述的方法专门用于在计算机系统上执行，例如，在硬件中，允许计算机系统以低延迟和低功耗执行平方根操作。

56. 发明授权

US09213639B2 Division of numerical values based on summations and memory mapping in computing systems 有权
标题翻译：基于计算系统中求和和内存映射的数值分割
公开(公告)号：US09213639B2
公开(公告)日：2015-12-15
申请号：US13626799
申请日：2012-09-25
申请人： Jeremy Branscome
发明人： Jeremy Branscome
IPC分类号： G06F12/06 , G06F7/535
CPC分类号： G06F12/0607 , G06F7/535 , G06F2207/5355 , G06F2207/5356
摘要： Divisions by numbers that are not divisible by two (2) can be performed in a computing system based on a summation that estimates and/or approximates the reciprocal of the dividing number or denominator value. By way of example, dividing by three (3) can be calculated based on a summation that approximates or estimates one third (⅓) represented as the sum of a selected group of the inverses of the powers of two (2) in a pattern, namely the sum of: ¼, 1/16, 1/64, 1/256, . . . ). Applications of the division techniques are virtually unlimited and include memory mapping of global memory addresses to memory channel addresses by dividing a global memory address into the number of memory channels, allowing memory mapping to be performed in an efficient manner even for large memory spaces using a number of memory channels that are not divisible by two, including prime numbers.
摘要翻译：不能被二（2）除尽的数字的划分可以在计算系统中基于估计和/或近似分割数或分母值的倒数的求和来执行。作为示例，可以基于近似或估计表示为模式中两（2）的幂的所选择的组的和的三分之一（1/3）的总和来计算除以三（3）即：¼，1/16，1/64，1/256，。。）。划分技术的应用实际上是无限制的，并且包括将全局存储器地址到存储器通道地址的存储器映射，通过将全局存储器地址划分为存储器通道的数量，允许以有效的方式执行存储器映射，即使对于使用不能被2整除的内存通道数，包括素数。

57. 发明授权

US08990278B1 Circuitry for computing mathematical functions 有权
标题翻译：用于计算数学函数的电路
公开(公告)号：US08990278B1
公开(公告)日：2015-03-24
申请号：US13275130
申请日：2011-10-17
申请人： Christopher M. Clegg
发明人： Christopher M. Clegg
IPC分类号： G06F1/02 , G06F7/38 , G06F7/552 , G06F7/544
CPC分类号： G06F7/544 , G06F7/535 , G06F7/5525 , G06F7/556 , G06F2207/5355 , G06F2207/5356
摘要： Methods and circuitry for evaluating reciprocal, square root, inverse square root, logarithm, and exponential functions of an input value, Y. In one embodiment, an approximate value, RA, of the reciprocal of Y is generated. One Newton-Raphson iteration is performed as a function of RA and Y, resulting in a truncated approximate value, R. R is multiplied by Y and 1 is subtracted, resulting in a reduced argument, A. A Taylor series evaluation of A is performed, resulting in an evaluated argument, B. B is multiplied by a post-processing factor for the final result.
摘要翻译：用于评估输入值Y的倒数，平方根，反平方根，对数和指数函数的方法和电路。在一个实施例中，生成Y的倒数的近似值RA。一个牛顿 - 拉夫逊迭代作为RA和Y的函数执行，产生一个截断的近似值，R被乘以Y，减去1，导致一个减少的参数A.执行A的泰勒级数评估，得到一个评估参数，B.B乘以最终结果的后处理因子。

58. 发明申请

US20120226730A1 System and Method for Testing Whether a Result is Correctly Rounded 有权
标题翻译：检查结果是否正确四舍五入的系统和方法
公开(公告)号：US20120226730A1
公开(公告)日：2012-09-06
申请号：US13038193
申请日：2011-03-01
申请人： Alexandru FIT-FLOREA
发明人： Alexandru FIT-FLOREA
IPC分类号： G06F7/552 , G06F7/38 , G06F7/44
CPC分类号： G06F7/483 , G06F7/4873 , G06F7/49942 , G06F7/5525 , G06F2207/5355 , G06F2207/5356
摘要： A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.
摘要翻译：公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

59. 发明申请

US20110289131A1 MACHINE DIVISION 有权
标题翻译：机械部
公开(公告)号：US20110289131A1
公开(公告)日：2011-11-24
申请号：US12785040
申请日：2010-05-21
申请人： Earl E. Swartzlander, JR. , Inwook Kong
发明人： Earl E. Swartzlander, JR. , Inwook Kong
IPC分类号： G06F7/44 , G06F7/552
CPC分类号： G06F7/535 , G06F2207/5355
摘要： Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.
摘要翻译：通常描述技术，其包括用分母除以分子的方法，装置，系统和/或装置。一些示例性方法可以包括选择存储在电子存储介质中的第一数值因子。至少部分地使用被配置为执行乘法的第一逻辑电路，第一数值因子可以乘以分子。第一数值因子也可以乘以分母。可以至少部分地基于第一数值因子和分母的单位和乘积之间的差的平方的近似来计算第二数值因子。至少部分地使用第一逻辑电路将第二数值因子乘以分子和第一数值因子的乘积，以产生分子和分母的商的近似。

60. 发明授权

US07921278B2 Early exit processing of iterative refinement algorithm using register dependency disable 失效
标题翻译：使用寄存器依赖关系禁用的迭代细化算法的早期退出处理
公开(公告)号：US07921278B2
公开(公告)日：2011-04-05
申请号：US12045313
申请日：2008-03-10
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30014 , G06F7/4873 , G06F7/535 , G06F9/30065 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F2207/5355 , G06F2207/5356
摘要： An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.
摘要翻译：迭代细化算法的“提前退出”除了禁用寄存器写入之外，还通过有效禁用更新指令的写依赖性停止之后的读取以及禁止这些指令的寄存器写使能，对于算法的其余部分启用这些指令。通过这样做，降低了算法的等待时间，并且性能得到提高，而没有另外需要的比较和分支指令的复杂性和潜在的差的性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式