基本信息:
- 专利标题： 감소된 면적을 갖는 승법식 제산 회로
- 专利标题（英）：Multiplicative division circuit with reduced area
- 专利标题（中）：具有减少面积的多路分段电路
- 申请号：KR1020127000695 申请日：2010-06-10
- 公开(公告)号：KR1020120017468A 公开(公告)日：2012-02-28
- 发明人： 한경남 , 텐카알렉산드르 , 트랜데이비드 , 켈리릭
- 申请人： 시놉시스, 인크.
- 申请人地址： *** E. Middlefield Rd., Mountain View, CA *****, U.S.A.
- 专利权人： 시놉시스, 인크.
- 当前专利权人： 시놉시스, 인크.
- 当前专利权人地址： *** E. Middlefield Rd., Mountain View, CA *****, U.S.A.
- 代理人： 특허법인코리아나
- 优先权： US12/488,956 2009-06-22; US61/185,929 2009-06-10
- 国际申请： PCT/US2010/038124 2010-06-10
- 国际公布： WO2010144673 2010-12-16
- 主分类号： G06F7/52
- IPC分类号： G06F7/52 ; G06F17/50
This technology is a reduced circuit area division circuit. Embodiment includes an integrated circuit for implementing multiplicative expression division of the dividend and the divisor input type. The integrated circuit includes a look-up table circuit and the multiplier circuit. A look-up table circuit provides an approximation of the reciprocal of the divisor input. Multiplier circuit receives an approximation of the quotient output of the dividend and the divisor input, and the input sections. At least one of the plurality of the multiplier circuit is multiplied by the product to implement the middle of the square circuit it can be reduced. That prevent the intermediate portion of a reduced number of multiplication circuits for multiplying the square can not equal any of the two squares and the multiplication circuit is limited to the same number of the same number.
公开/授权文献:
- KR101411683B1 감소된 면적을 갖는 승법식 제산 회로 公开/授权日：2014-06-25
信息查询:
EspacenetIPC结构图谱:
| G | 物理 |
| --G06 | 计算；推算；计数 |
| ----G06F | 电数字数据处理 |
| ------G06F7/00 | 通过待处理的数据的指令或内容进行运算的数据处理的方法或装置 |
| --------G06F7/02 | .比较数字值的 |
| ----------G06F7/48 | ..应用非形成接触器件的，例如，电子管、固体器件；应用非特定的器件的 |
| ------------G06F7/52 | ...进行乘法的；进行除法的 |