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51. 发明授权

US08125002B2 Semiconductor device and inverter circuit having the same 有权
标题翻译：半导体器件和逆变器电路具有相同的功能
公开(公告)号：US08125002B2
公开(公告)日：2012-02-28
申请号：US12289852
申请日：2008-11-06
申请人： Yutaka Fukuda , Yukio Tsuzuki
发明人： Yutaka Fukuda , Yukio Tsuzuki
IPC分类号： H01L29/43 , H01L29/45
CPC分类号： H01L29/7397 , H01L27/0664 , H01L27/0694 , H01L2924/0002 , H03K2217/0027 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.
摘要翻译：半导体器件包括半导体衬底，形成于半导体衬底的绝缘栅晶体管，形成于半导体衬底的二极管，和形成于半导体衬底的控制晶体管。绝缘栅极晶体管的第一电流端子在高电位侧耦合到二极管的阴极。绝缘栅晶体管的第二电流端子在低电位侧耦合到二极管的阳极。控制晶体管被配置为当二极管导通电流时，通过减小绝缘栅极晶体管的栅极端子的电位来关断绝缘栅极晶体管。

52. 发明授权

US08080853B2 Semiconductor device including insulated gate bipolar transistor and diode 有权
标题翻译：半导体器件包括绝缘栅双极晶体管和二极管
公开(公告)号：US08080853B2
公开(公告)日：2011-12-20
申请号：US12654228
申请日：2009-12-15
申请人： Yukio Tsuzuki , Hiromitsu Tanabe , Kenji Kouno
发明人： Yukio Tsuzuki , Hiromitsu Tanabe , Kenji Kouno
IPC分类号： H01L29/94
CPC分类号： H01L27/0664 , H01L29/0619 , H01L29/0834 , H01L29/7395 , H01L29/7397 , H03K17/0828 , H03K17/145
摘要： A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.
摘要翻译：半导体器件包括半导体衬底中的垂直IGBT和垂直续流二极管。在半导体衬底的第一表面侧部分设置有多个基极区域，并且多个集电极区域和多个阴极区域交替地设置在半导体衬底的第二表面侧部分中。基极区域包括在垂直IGBT处于工作状态时设置通道的多个区域。半导体衬底的第一侧部分包括多个IGBT区域，每个IGBT区域各自位于相邻的两个沟道之间，包括与发射极电气耦合的一个基极区域，并与阴极区域中的一个相对。 IGBT区域包括多个窄区域和多个宽区域。

53. 发明授权

US07692221B2 Semiconductor device having IGBT element 有权
标题翻译：具有IGBT元件的半导体器件
公开(公告)号：US07692221B2
公开(公告)日：2010-04-06
申请号：US11714201
申请日：2007-03-06
申请人： Yoshihiko Ozeki , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Yukio Tsuzuki
IPC分类号： H01L27/088
CPC分类号： H01L29/0619 , H01L29/7397
摘要： A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.
摘要翻译：在半导体衬底上形成具有绝缘栅双极晶体管（IGBT）的半导体器件。在基板的第一表面上形成基极区域和发射极，同时在基板的第二表面上形成集电极层。在IGBT周围的第一表面上形成具有低击穿电压的区域，并且在具有低击穿电压的区域附近形成载流子收集区域。由于在具有低击穿电压的区域中发生击穿，因此防止IGBT由于雪崩现象而分解，并且通过载流子收集区域收集击穿电流的载流子。通过形成用于抑制具有低击穿电压的区域周围的电场浓度的保护环，进一步有效地防止了IGBT的击穿。

54. 发明授权

US07667269B2 Trench gate type semiconductor device 有权
标题翻译：沟槽型半导体器件
公开(公告)号：US07667269B2
公开(公告)日：2010-02-23
申请号：US11398551
申请日：2006-04-06
申请人： Yukio Tsuzuki , Norihito Tokura , Yoshihiko Ozeki , Kensaku Yamamoto
发明人： Yukio Tsuzuki , Norihito Tokura , Yoshihiko Ozeki , Kensaku Yamamoto
IPC分类号： H01L23/62
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 μm.
摘要翻译：一种半导体器件包括：第一半导体层; 在所述第一半导体层上的第二半导体层; 第二半导体层上的第三半导体层; 在所述第三半导体层的一部分中的第四半导体层; 穿过第四半导体层和第三半导体层并到达第二半导体层的沟槽; 沟槽内壁上的栅极绝缘膜; 在沟槽中的栅极绝缘膜上的栅电极; 第一电极; 和第二电极。沟槽包括具有曲率半径等于或小于0.5μm的曲面的底部。

55. 发明授权

US07498634B2 Semiconductor device having IGBT and diode 有权
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US07498634B2
公开(公告)日：2009-03-03
申请号：US11649367
申请日：2007-01-04
申请人： Yukio Tsuzuki , Norihito Tokura
发明人： Yukio Tsuzuki , Norihito Tokura
IPC分类号： H01L29/76
CPC分类号： H01L27/0664 , H01L29/0834 , H01L29/7397 , H01L29/861
摘要： A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.
摘要翻译：一种半导体器件包括：具有第一面和第二面的衬底; IGBT; 和二极管。衬底包括第一层，第一层上的第二层，第二层上的第一侧N区，第一层的第二侧上的第二侧N和P区，用于栅极的第一沟槽中的第一电极电极，第一侧N区域上的第二电极和用于发射电极和阳极电极的第二沟槽中，以及在第二侧的第三电极N和用于集电极和阴极的P区域。第一沟槽穿过第一侧N区和第二层，并到达第一层。第二沟槽穿过第一侧N区域并到达第二层。

56. 发明申请

US20080315248A1 Semiconductor Device Having Igbt Cell and Diode Cell and Method for Designing the Same 有权
标题翻译：具有Igbt电池和二极管电池的半导体器件及其设计方法
公开(公告)号：US20080315248A1
公开(公告)日：2008-12-25
申请号：US11885334
申请日：2007-03-20
申请人： Norihito Tokura , Yukio Tsuzuki , Kenji Kouno
发明人： Norihito Tokura , Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L29/739 , G06F17/50
CPC分类号： H01L29/7395 , H01L27/0664 , H01L29/861
摘要： A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ρ1 and a thickness L1 of the first layer, a resistivity ρ2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (ρ1/ρ2)×(L1·L2/W22)
摘要翻译：半导体器件包括：半导体衬底; IGBT单元; 和二极管单元。衬底包括在第一表面上的第一层，相邻地布置在衬底的第二表面上的第二层和第三层以及在第一层和第二层和第三层之间的第四层。第一层提供了IGBT单元和二极管单元的漂移层。第二层提供IGBT单元的集电极层。第三层提供二极管单元的一个电极连接层。第一层的电阻率rho1和第一层的厚度L1，第四层的电阻率rho2和厚度L2以及第二层在基板平面上的最小宽度W2的一半具有（rho1 / rho2）× （L1.L2 / W22）<1.6。

57. 发明授权

US07348244B2 Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07348244B2
公开(公告)日：2008-03-25
申请号：US11345310
申请日：2006-02-02
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

58. 发明授权

US07026215B2 Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07026215B2
公开(公告)日：2006-04-11
申请号：US11087758
申请日：2005-03-24
申请人： Takaaki Aoki , Yukio Tsuzuki
发明人： Takaaki Aoki , Yukio Tsuzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/28194 , H01L21/28202 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/513 , H01L29/518 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.
摘要翻译：半导体器件包括半导体衬底，用于作为晶体管操作的衬底的表面部分中的单元区域，在衬底上具有栅极引线图案的栅极引线布线区域，从衬底的表面部分延伸的沟槽沟槽的内表面上的氧化膜，以及沟槽中的栅电极，至少与衬底的氧化膜绝缘。在栅极引线布线区域处沟槽的侧壁的主要部分的形成速度大于在单元区域处的沟槽的侧壁的主要部分的速度，使得栅极处的氧化物膜的厚度引线布线区域大于单元区域。

59. 发明授权

US4963505A Semiconductor device and method of manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4963505A
公开(公告)日：1990-10-16
申请号：US260997
申请日：1988-10-21
申请人： Tetsuo Fujii , Susumu Kuroyanagi , Yukio Tsuzuki
发明人： Tetsuo Fujii , Susumu Kuroyanagi , Yukio Tsuzuki
IPC分类号： H01L21/762 , H01L21/763 , H01L27/088
CPC分类号： H01L21/76248 , H01L21/762 , H01L21/76264 , H01L21/763 , H01L21/76272 , H01L21/76275 , H01L21/76286 , H01L27/088 , Y10S148/012 , Y10S438/969
摘要： Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region. This semiconductor device has an additional characteristics in that another semiconductor device using another main surface of the substrate as the electrode is provided on the surface of the substrate and the single cyrstal semiconductor layer, and the polycrystalline semiconductor layer serves to terminate the electric line of force emitted from the substrate, and therefore, the single crystal semiconductor layer mounted on the polycrystalline semiconductor layer is not affected by the electric line of force. Consequently, a semiconductor device which can operate effectively without being influenced by variations of the electric potential in the substrate can be obtained, and further, an intelligent type power device can be formed in which the power semiconductor device and the semiconductor device controlling the power device are formed in the same substrate but are completely isolated from each other.
摘要翻译：公开了一种半导体器件，其包括基板，形成在基板中或基板的主表面上的预定区域处的绝缘膜，形成在至少绝缘膜上的多晶半导体层，形成在基板上的单晶半导体层至少多晶半导体层，通过多晶半导体层形成为从单晶半导体层的顶部主表面延伸到至少绝缘膜的表面的隔离区，以将形成在单晶半导体中的部分电隔离所述隔离区域与形成在所述单晶半导体层中的不被所述隔离区域包围的另一部分包围的至少一个半导体器件形成在由所述隔离区域包围的部分内。该半导体器件具有另外的特征，即在基板的表面和单个硅谷半导体层上设置另一个使用基板的另一个主表面作为电极的半导体器件，并且多晶半导体层用于终止电力线从衬底发出的，因此，安装在多晶半导体层上的单晶半导体层不受电力线的影响。因此，可以获得能够有效地工作而不受基板中电位变化的影响的半导体器件，并且还可以形成智能型功率器件，其中功率半导体器件和控制功率器件的半导体器件形成在相同的基板中，但彼此完全隔离。

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