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51. 发明申请

US20060244042A1 Split gate type nonvolatile memory device and method of fabricating the same 失效
标题翻译：分闸式非易失性存储装置及其制造方法
公开(公告)号：US20060244042A1
公开(公告)日：2006-11-02
申请号：US11413640
申请日：2006-04-28
申请人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
发明人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
摘要翻译：在分闸式非易失存储器件及其制造方法中，辅助层图案设置在半导体衬底的源极区域上。由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

52. 发明申请

US20150155024A1 MAGNETIC MEMORY DEVICES INCLUDING SHARED LINES 有权
标题翻译：包含共享线的磁记录设备
公开(公告)号：US20150155024A1
公开(公告)日：2015-06-04
申请号：US14448717
申请日：2014-07-31
申请人： Bo-Young SEO , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
发明人： Bo-Young SEO , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659
摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
摘要翻译：磁存储器件包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。还描述了相关系统和操作方法。

53. 发明授权

US09318181B2 Magnetic memory devices including shared lines 有权
标题翻译：包括共享线路的磁存储器件
公开(公告)号：US09318181B2
公开(公告)日：2016-04-19
申请号：US14448717
申请日：2014-07-31
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659
摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
摘要翻译：磁存储装置包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。还描述了相关系统和操作方法。

54. 发明申请

US20150179244A1 Magnetic Memory Devices Including Magnetic Memory Cells Having Opposite Magnetization Directions 有权
标题翻译：包括具有相反磁化方向的磁记忆体的磁存储器件
公开(公告)号：US20150179244A1
公开(公告)日：2015-06-25
申请号：US14509756
申请日：2014-10-08
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.
摘要翻译：磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。还讨论了相关的操作方法。

55. 发明授权

US09330745B2 Magnetic memory devices including magnetic memory cells having opposite magnetization directions 有权
标题翻译：磁存储器件包括具有相反磁化方向的磁存储单元
公开(公告)号：US09330745B2
公开(公告)日：2016-05-03
申请号：US14509756
申请日：2014-10-08
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.
摘要翻译：磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。还讨论了相关的操作方法。

56. 发明授权

US08110873B2 High voltage transistor 失效
标题翻译：高压晶体管
公开(公告)号：US08110873B2
公开(公告)日：2012-02-07
申请号：US12339448
申请日：2008-12-19
申请人： Sung-Gon Choi , Hee-Seog Jeon
发明人： Sung-Gon Choi , Hee-Seog Jeon
IPC分类号： H01L21/76
CPC分类号： H01L29/0847 , H01L21/76895 , H01L29/0692 , H01L29/402 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7831 , H01L29/7833 , H01L29/7835
摘要： A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.
摘要翻译：一种高电压晶体管，包括限定有源区的衬底，所述有源区中的第一杂质区和第二杂质区以及所述第一和第二杂质区之间的第三杂质区，以及所述有源区上的第一栅电极在第一杂质区域和第三杂质区域之间的有源区域上的第二栅电极和第二杂质区域之间的有源区域上的第二栅电极。

57. 发明申请

US20060092705A1 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US20060092705A1
公开(公告)日：2006-05-04
申请号：US11256554
申请日：2005-10-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.
摘要翻译：提供具有多位非易失性存储单元的半导体器件。半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。多个晶体管每个包括至少一个控制栅极和至少一个电荷存储区域。电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

58. 发明授权

US06255716B1 Bipolar junction transistors having base electrode extensions 失效
标题翻译：具有基极扩展的双极结晶体管
公开(公告)号：US06255716B1
公开(公告)日：2001-07-03
申请号：US09502343
申请日：2000-02-10
申请人： Hee-Seog Jeon
发明人： Hee-Seog Jeon
IPC分类号： H01L27102
CPC分类号： H01L29/66272 , H01L29/42304
摘要： Methods of forming bipolar junction transistors having preferred base electrode extensions include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to define a L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein. This diffusion step can be performed in a carefully controlled manner to limit the extent to which the extrinsic base region dopants adversely effect the electrical characteristics of surrounding regions or contribute to parasitic capacitance. Dopants of second conductivity type are also preferably implanted into the substrate to define an intrinsic base region therein. This dopant implant step is preferably performed using the base electrode spacer as an implant mask. Accordingly, the base electrode spacer is used advantageously as an etching mask and as a dopant implantation mask. An emitter region of first conductivity type is also preferably formed in the intrinsic base region.
摘要翻译：形成具有优选的基极延伸部的双极结型晶体管的方法包括以下步骤：在衬底的表面上形成第二导电类型的基极（例如P型）。然后形成与基极的侧壁接触的导电基极延伸层。基极延伸层可以是掺杂的或未掺杂的。然后，在与基极的侧壁相对的导电基极延伸层上形成电绝缘基极间隔物。然后，使用基极间隔件作为蚀刻掩模，蚀刻导电基极延伸层以限定L形基极延伸。然后，第二导电类型的掺杂剂从基极通过基极延伸扩散到衬底中以在其中限定非本征基区。该扩散步骤可以以仔细控制的方式进行，以限制外部碱性区域掺杂对其周围区域的电特性的不利影响或有助于寄生电容的程度。也优选将第二导电类型的掺杂剂注入到衬底中以在其中限定其内部基极区域。该掺杂剂注入步骤优选使用基极间隔物作为植入掩模进行。因此，基极隔离器有利地用作蚀刻掩模和掺杂剂注入掩模。也优选在本征基区形成第一导电类型的发射极区域。

59. 发明授权

US08698239B2 Semiconductor devices having asymmetric doped regions and methods of fabricating the same 有权
标题翻译：具有不对称掺杂区域的半导体器件及其制造方法
公开(公告)号：US08698239B2
公开(公告)日：2014-04-15
申请号：US13352194
申请日：2012-01-17
申请人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
发明人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
IPC分类号： H01L29/66 , H01L29/423 , H01L29/788 , H01L21/28 , H01L27/115 , H01L27/02
CPC分类号： H01L29/42328 , H01L21/28273 , H01L27/0207 , H01L27/11504 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L29/7883
摘要： A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.
摘要翻译：半导体器件包括在衬底中的有源区域，与有源区域交叉并顺序地彼此平行布置的第一至第三栅极结构，位于第一和第二栅极结构之间的有源区域中的第一掺杂区域，并且具有第一水平宽度和第一深度和在第二和第三栅极结构之间的有源区域中的第二掺杂区域，并且具有第二水平宽度和第二深度。第二水平宽度大于第一水平宽度，第二深度比第一深度浅。彼此相邻的第一和第二栅极结构之间的距离小于彼此相邻的第二和第三栅极结构之间的距离。还描述了相关的制造方法。

60. 发明申请

US20120044772A1 NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY 有权
标题翻译：非易失性存储器件，系统和细胞阵列
公开(公告)号：US20120044772A1
公开(公告)日：2012-02-23
申请号：US13114120
申请日：2011-05-24
申请人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Ji-Do Ryu
发明人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Ji-Do Ryu
IPC分类号： G11C16/10 , G11C16/06 , G11C16/04
CPC分类号： G11C16/06 , G11C16/0483
摘要： A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.
摘要翻译：一种非易失性存储单元阵列，包括由施加到扇区选择线的电压控制的扇区选择晶体管，与扇区选择晶体管串联连接的第一至第四存储器单元，连接在第一存储单元与第二存储单元之间的第一公共源极线以及连接在第三存储单元和第四存储单元之间并与第一公共源极线分离的第二公共源极线。向第一公共源极线施加第一电压，并且将不同于第一电压的第二电压施加到第二公共源极线。

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