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51. 发明授权

US06636950B1 Computer architecture for shared memory access 失效
标题翻译：用于共享内存访问的计算机体系结构
公开(公告)号：US06636950B1
公开(公告)日：2003-10-21
申请号：US09300641
申请日：1999-04-27
申请人： Arvind Mithal , Xiaowei Shen , Lawrence Rogel
发明人： Arvind Mithal , Xiaowei Shen , Lawrence Rogel
IPC分类号： G06F1200
CPC分类号： G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F12/0817 , G06F12/0826 , G06F12/084
摘要： A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.
摘要翻译：包括分层存储器系统和一个或多个处理器的计算机体系结构。处理器执行存储器访问指令，其语义是根据存储器系统的层次结构定义的。也就是说，不是试图保持所有处理器共享存储器系统的错觉，使得一个处理器所做的改变对于其他处理器是立即可见的，所以存储器访问指令明确地解决对处理器特定存储器的访问以及数据传输在处理器特定的存储器和共享存储器系统之间。存储器系统的各种替代实施例与这些指令兼容。这些替代实施例不改变使用存储器访问指令的计算机程序的语义含义，而是允许不同的方法来实现数据从一个处理器到另一处理器的实际传递。

52. 发明授权

US09141547B2 Architecture support of best-effort atomic transactions for multiprocessor systems 有权
标题翻译：支持多处理器系统的尽力原子事务
公开(公告)号：US09141547B2
公开(公告)日：2015-09-22
申请号：US11968854
申请日：2008-01-03
申请人： Xiaowei Shen
发明人： Xiaowei Shen
IPC分类号： G06F9/46 , G06F12/08 , G06F9/30
CPC分类号： G06F12/0833 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： An atomic transaction includes one or more memory access operations that are completed atomically. A Best-Effort Transaction (BET) system makes its best effort to complete each atomic transaction without guaranteeing completion of all atomic transactions. When an atomic transaction is aborted, BET may provide software with appropriate runtime information such as cause of the abortion. With proper coherence layer enhancements, BET can be implemented efficiently for multiprocessor systems, using caches as buffers for data accessed by atomic transactions. Furthermore, with appropriate fairness support, forward progress can be guaranteed for atomic transactions that incur no buffer overflow.
摘要翻译：原子事务包括原子地完成的一个或多个存储器访问操作。最佳努力交易（BET）系统尽最大努力完成每个原子事务，而不保证完成所有原子事务。当原子事务中止时，BET可以向软件提供适当的运行时信息，例如堕胎的原因。通过适当的相干层增强功能，可以高效地为多处理器系统实施BET，将缓存用作由原子事务访问的数据的缓冲区。此外，通过适当的公平支持，可以保证不会产生缓冲区溢出的原子事务的前进进度。

53. 发明授权

US08789028B2 Memory access monitoring 失效
标题翻译：内存访问监控
公开(公告)号：US08789028B2
公开(公告)日：2014-07-22
申请号：US11478743
申请日：2006-06-30
申请人： Xiaowei Shen , Peter F. Sweeney
发明人： Xiaowei Shen , Peter F. Sweeney
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3471 , G06F8/443 , G06F2201/88
摘要： A computer-implemented method for memory access monitoring, implemented by a managed runtime environment computer system including a controller that monitors application behavior and determines actions to be taken to change a behavior of an application, and a runtime, dynamic compiler that analyzes the application and generates code sequences to access a memory access monitoring (MAM) mechanism, includes determining monitor information of a plurality of fields of a memory block to drive an optimization of the application.
摘要翻译：一种用于存储器访问监视的计算机实现的方法，由管理的运行时环境计算机系统实现，所述计算机系统包括监视应用程序行为并确定要改变应用程序行为的控制器的控制器，以及分析应用程序的运行时，动态编译器，以及生成用于访问存储器访问监视（MAM）机制的代码序列，包括确定存储器块的多个字段的监视器信息以驱动应用的优化。

54. 发明申请

US20090119667A1 METHOD AND APPARATUS FOR IMPLEMENTING TRANSACTION MEMORY 审中-公开
标题翻译：实施交易记忆的方法和装置
公开(公告)号：US20090119667A1
公开(公告)日：2009-05-07
申请号：US12265788
申请日：2008-11-06
申请人： Rui Hou , Xiaowei Shen , Hua Yong Wang
发明人： Rui Hou , Xiaowei Shen , Hua Yong Wang
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/467
摘要： A method and apparatus for implementing transactional memory (TM). The method includes: allocating a hardware-based transaction footprint recorder to the transaction, for recording footprints of the transaction when a transaction is begun; determining that the transaction is to be switched out; and switching out the transaction, where the footprints of the switched-out transaction are still kept in the hardware-based transaction footprint recorder. According to the present invention, transaction switching is supported by TM, and the cost of conflict detection between an active transaction and a switched-out transaction is greatly reduced since the footprints of the switched-out transaction are still kept in the hardware-based transaction footprint recorder.
摘要翻译：一种用于实现事务存储器（TM）的方法和装置。该方法包括：将分配基于硬件的交易足迹记录器分配给交易，用于在交易开始时记录交易的足迹; 确定交易将被切换; 并切换交易，其中所述切换交易的足迹仍保留在基于硬件的交易记录记录器中。根据本发明，由TM支持交易切换，并且大大减少了活动事务和切换事务之间的冲突检测的成本，因为切换事务的覆盖区仍然保留在基于硬件的事务中足迹录像机。

55. 发明申请

US20090083492A1 COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS 审中-公开
标题翻译： COST-CONSCIOUS PRE-CMPE CACHE LINE位移和移动机制
公开(公告)号：US20090083492A1
公开(公告)日：2009-03-26
申请号：US12272612
申请日：2008-11-17
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude A. Rivers , John T. Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/128 , Y02D10/13
摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.
摘要翻译：一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

56. 发明申请

US20080282032A1 ADAPTIVE MECHANISMS AND METHODS FOR SUPPLYING VOLATILE DATA COPIES IN MULTIPROCESSOR SYSTEMS 失效
标题翻译：自适应机制和方法供应多处理器系统中的挥发性数据复制
公开(公告)号：US20080282032A1
公开(公告)日：2008-11-13
申请号：US11458192
申请日：2006-07-18
申请人： Xiaowei Shen , Man Cheuk Ng , Aaron Christoph Sawdey
发明人： Xiaowei Shen , Man Cheuk Ng , Aaron Christoph Sawdey
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F2212/1016 , G06F2212/507
摘要： In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.
摘要翻译：在具有存储器层次结构的计算机系统中，当高级缓存将数据拷贝提供给低级缓存时，共享副本可以是易失性的或非易失性的。当数据拷贝稍后从低级缓存中替换时，如果数据拷贝是非易失性的，则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。高级缓存可以采用易失性预测机制，其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问，则使用非易失性拷贝。此外，低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制，或者根据某种降级策略将数据拷贝从非易失性变为不稳定。

57. 发明申请

US20080082756A1 Mechanisms and methods of using self-reconciled data to reduce cache coherence overhead in multiprocessor systems 审中-公开
标题翻译：使用自协调数据来减少多处理器系统中的缓存一致性开销的机制和方法
公开(公告)号：US20080082756A1
公开(公告)日：2008-04-03
申请号：US11541911
申请日：2006-10-02
申请人： Xiaowei Shen
发明人： Xiaowei Shen
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/082 , G06F2212/507
摘要： A system for maintaining cache coherence includes a plurality of caches, wherein at least a first cache and a second cache of the plurality of caches are connected via an interconnect network, a memory for storing data of a memory address, the memory connected to the interconnect network, and a plurality of coherence engines including a self-reconciled data prediction mechanism, wherein a first coherence engine of the plurality of coherence engines is operatively associated with the first cache, and a second coherence engine of the plurality of coherence engines is operatively associated with the second cache, wherein the first cache requests the data of the memory address in case of a cache miss, and receives one of a regular data copy or a self-reconciled data copy according to the self-reconciled data prediction mechanism.
摘要翻译：用于维持高速缓存一致性的系统包括多个高速缓存，其中多个高速缓存中的至少第一高速缓存和第二高速缓存经由互连网络连接，存储器，用于存储存储器地址的数据，连接到互连的存储器网络以及包括自协调数据预测机制的多个相干引擎，其中所述多个相干引擎中的第一相干引擎与所述第一高速缓存可操作地相关联，并且所述多个相干引擎中的第二相干引擎可操作地相关联具有第二高速缓存，其中第一高速缓存在高速缓存未命中的情况下请求存储器地址的数据，并且根据自协调数据预测机制接收常规数据副本或自协调数据副本中的一个。

58. 发明申请

US20060288173A1 Architecture support of best-effort atomic transactions for multiprocessor systems 有权
公开(公告)号：US20060288173A1
公开(公告)日：2006-12-21
申请号：US11156913
申请日：2005-06-20
申请人： Xiaowei Shen
发明人： Xiaowei Shen
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： An atomic transaction includes one or more memory access operations that are completed atomically. A Best-Effort Transaction (BET) system makes its best effort to complete each atomic transaction without guaranteeing completion of all atomic transactions. When an atomic transaction is aborted, BET may provide software with appropriate runtime information such as cause of the abortion. With proper coherence layer enhancements, BET can be implemented efficiently for multiprocessor systems, using caches as buffers for data accessed by atomic transactions. Furthermore, with appropriate fairness support, forward progress can be guaranteed for atomic transactions that incur no buffer overflow.

59. 发明申请

US20060248287A1 Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures 审中-公开
标题翻译：在非均匀缓存存储器架构中减少延迟和窥探成本的方法和安排
公开(公告)号：US20060248287A1
公开(公告)日：2006-11-02
申请号：US11118130
申请日：2005-04-29
申请人： Alper Buyuktosunoglu , Zhigang Hu , Jude Rivers , John Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Zhigang Hu , Jude Rivers , John Robinson , Xiaowei Shen , Vijayalakshmi Srinivasan
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F12/0897 , G06F2212/2542 , G06F2212/271
摘要： Arrangements and methods for providing cache management. Preferably, a buffer arrangement is provided that is adapted to record incoming data into a first cache memory from a second cache memory, convey a data location in the first cache memory upon a prompt for corresponding data, in the event of a hit in the first cache memory, and refer to the second cache memory in the event of a miss in the first cache memory.
摘要翻译：提供缓存管理的安排和方法。优选地，提供缓冲器装置，其适于将来自第二高速缓冲存储器的输入数据记录到第一高速缓冲存储器中，在第一高速缓冲存储器中的第一高速缓冲存储器高速缓冲存储器，并且在第一高速缓冲存储器中未命中的情况下参考第二高速缓冲存储器。

60. 发明申请

US20060106995A1 Methods to maintain triangle ordering of coherence messages 失效
标题翻译：维持连贯消息三角形排序的方法
公开(公告)号：US20060106995A1
公开(公告)日：2006-05-18
申请号：US10989755
申请日：2004-11-16
申请人： Xiaowei Shen
发明人： Xiaowei Shen
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0815
摘要： We present a triangle ordering mechanism that maintains triangle ordering of coherence messages in SMP systems. If cache A sends a multicast message to caches B and C, and if cache B sends a message to cache C after receiving and processing the multicast message from cache A, the triangle ordering mechanism ensures that cache C processes the multicast message from cache A before processing the message from cache B. The triangle ordering mechanism enables efficient snoopy cache coherence in SMP systems in which caches communicate with each other via message-passing networks. A modified version of the triangle ordering mechanism categorizes coherence messages into non-overlapping sequencing classes, and ensures triangle ordering for coherence messages in the same sequencing class. The modified triangle ordering mechanism can significantly reduce potential performance degradation due to false waiting.
摘要翻译：我们提出一种维护SMP系统中相干消息的三角形排序的三角形排序机制。如果缓存A向缓存B和C发送多播消息，并且如果缓存B在从高速缓存A接收并处理多播消息之后向高速缓存C发送消息，则三角排序机制确保高速缓存C在高速缓存A之前处理来自高速缓存A的多播消息处理来自高速缓存B的消息。三角排序机制使得高速缓存在SMP系统中的高速缓存一致性，其中高速缓存通过消息传递网络彼此通信。三角形排序机制的修改版本将相干消息分类为非重叠排序类，并确保相同排序类中的相干消息的三角形排序。改进的三角形排序机制可以显着降低由于假等待引起的潜在性能下降。

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