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51. 发明申请

US20130194031A1 DATA-DRIVEN CHARGE-PUMP TRANSMITTER FOR DIFFERENTIAL SIGNALING 有权
标题翻译：用于差分信号的数据驱动充电泵发射器
公开(公告)号：US20130194031A1
公开(公告)日：2013-08-01
申请号：US13361843
申请日：2012-01-30
申请人： John W. POULTON , Thomas Hastings Greer, III , William J. Dally
发明人： John W. POULTON , Thomas Hastings Greer, III , William J. Dally
IPC分类号： G05F3/02
CPC分类号： H04L25/0272 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： One embodiment of the present invention sets forth a mechanism for transmitting and receiving differential signals. A transmitter combines a direct current (DC) to DC converter including a capacitor with a 2:1 multiplexer to drive a pair of differential signaling lines. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different differential signaling pairs. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.
摘要翻译：本发明的一个实施例提出了用于发送和接收差分信号的机制。发射机将直流（DC）到DC转换器组合，包括具有2：1多路复用器的电容器，以驱动一对差分信号线。发射机驱动一对对地面电源电平对称的电压。信号电流返回到接地平面，以最小化作为不同差分信号对之间串扰源的噪声的产生。通过电源引入的噪声与数据的切换速率相关，并且可以使用均衡器电路来减小。

52. 发明授权

US08243847B2 Digital transmitter 有权
标题翻译：数字发射机
公开(公告)号：US08243847B2
公开(公告)日：2012-08-14
申请号：US12571582
申请日：2009-10-01
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/04 , H04L25/03 , H04L27/00 , H03K5/156
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
摘要翻译：提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。优选的均衡器包括使用查找表的FIR转换滤波器。包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

53. 发明申请

US20110135032A1 DIGITAL TRANSMITTER 有权
标题翻译：数字发射机
公开(公告)号：US20110135032A1
公开(公告)日：2011-06-09
申请号：US13027893
申请日：2011-02-15
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/00
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
摘要翻译：提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。优选的均衡器包括使用查找表的FIR转换滤波器。包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

54. 发明授权

US07924963B2 Digital Transmit phase trimming 有权
标题翻译：数字发送相位修整
公开(公告)号：US07924963B2
公开(公告)日：2011-04-12
申请号：US12628982
申请日：2009-12-01
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L7/00
CPC分类号： H04J3/0685 , H03M9/00 , H04L7/0037
摘要： A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.
摘要翻译：电路具有相位调整电路，通过根据控制信号调整第一时钟信号来产生经调整的时钟信号。多路复用器在多个第一数据线上接收输入数据信号，并根据多个第二时钟信号输出至少一个第二数据线输出数据信号。定时测量电路在至少一个第二数据线上确定至少一个输出数据信号的至少一个定时参数，并根据至少一个定时参数与期望值的偏差产生控制信号。

55. 发明授权

US07706464B2 Digital transmitter 失效
公开(公告)号：US07706464B2
公开(公告)日：2010-04-27
申请号：US11514510
申请日：2006-08-31
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/04
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

56. 发明授权

US07602858B2 Digital transmitter 有权
公开(公告)号：US07602858B2
公开(公告)日：2009-10-13
申请号：US11514460
申请日：2006-08-31
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L25/03
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

57. 发明授权

US07602857B2 Digital transmitter 有权
公开(公告)号：US07602857B2
公开(公告)日：2009-10-13
申请号：US11514577
申请日：2006-08-31
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L25/03
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

58. 发明申请

US20090210682A1 DATA TRANSFER BUS COMMUNICATION USING SINGLE REQUEST TO PERFORM COMMAND AND RETURN DATA TO DESTINATION INDICATED IN CONTEXT TO ALLOW THREAD CONTEXT SWITCH 有权
标题翻译：数据传输总线通信使用单次请求执行命令并将数据返回到目的地，显示为允许上下文切换
公开(公告)号：US20090210682A1
公开(公告)日：2009-08-20
申请号：US12429655
申请日：2009-04-24
申请人： Robert GELINAS , W. Patrick Hays , Sol Katzman , William J. Dally
发明人： Robert GELINAS , W. Patrick Hays , Sol Katzman , William J. Dally
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/48 , G06F9/4881
摘要： Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
摘要翻译：用于在处理系统中的线程之间管理上下文切换的系统和方法。处理器可以使用单独的上下文寄存器在线程之间执行上下文切换。上下文切换允许处理器从处理等待数据的线程切换到准备进行额外处理的线程。该处理器包括具有条目的控制寄存器，其可以指示相关联的上下文正在等待来自外部源的数据。

59. 发明授权

US07564920B1 Digital transmitter 有权
标题翻译：数字发射机
公开(公告)号：US07564920B1
公开(公告)日：2009-07-21
申请号：US11514515
申请日：2006-08-31
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/0272 , H04L25/0282 , H04L25/03885
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
摘要翻译：提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。优选的均衡器包括使用查找表的FIR转换滤波器。包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

60. 发明授权

US07529915B2 Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source 有权
标题翻译：具有多个上下文控制寄存器集的上下文切换处理器，包括写入地址寄存器，用于识别用于等待上下文存储来自外部源的返回数据的目的地寄存器
公开(公告)号：US07529915B2
公开(公告)日：2009-05-05
申请号：US11552640
申请日：2006-10-25
申请人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
发明人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
IPC分类号： G06F9/46
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/48 , G06F9/4881
摘要： Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
摘要翻译：用于在处理系统中的线程之间管理上下文切换的系统和方法。处理器可以使用单独的上下文寄存器在线程之间执行上下文切换上下文切换允许处理器从处理等待数据的线程切换到准备进行额外处理的线程。该处理器包括具有条目的控制寄存器，其可以指示相关联的上下文正在等待来自外部源的数据。

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