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51. 发明授权

US06859913B2 Representing a simulation model using a hardware configuration database 失效
标题翻译：表示使用硬件配置数据库的仿真模型
公开(公告)号：US06859913B2
公开(公告)日：2005-02-22
申请号：US10041753
申请日：2002-01-07
申请人： Timothy J. Fennell , William R. Wheeler
发明人： Timothy J. Fennell , William R. Wheeler
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method includes sending a query from graphical user interface to a hardware configuration database. The query requests information located within a simulation model. The hardware configuration database including locations of hardware devices. The hardware devices represent functional processes. The method also includes searching the functional processes to locate the information and directly accessing the information in the simulation model from the graphical user interface without assistance from the hardware configuration database.
摘要翻译：一种方法包括将查询从图形用户界面发送到硬件配置数据库。查询请求位于模拟模型内的信息。硬件配置数据库包括硬件设备的位置。硬件设备代表功能过程。该方法还包括搜索功能过程以定位信息，并且在没有硬件配置数据库的帮助下从图形用户界面直接访问模拟模型中的信息。

52. 发明授权

US06823438B2 Method for memory allocation and management using push/pop apparatus 失效
标题翻译：使用push / pop设备进行内存分配和管理的方法
公开(公告)号：US06823438B2
公开(公告)日：2004-11-23
申请号：US10746876
申请日：2003-12-23
申请人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
发明人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.
摘要翻译：一种用于具有数字处理系统的存储器分配的装置和方法，包括第一存储体，硬件寄存器和配置为将硬件寄存器的内容写入第一存储体中的存储器地址的处理电路，并且将存储器地址到硬件寄存器。在一个实施例中，可以在第一存储体中保持包含存储器指针值的指针列表。第一存储体可以包含相关联的数据缓冲器，并且第二存储体可以包含相应的数据缓冲器，使得可以从单个存储器指针值定位相关联的数据缓冲器和对应的数据缓冲器。

53. 发明授权

US06708321B2 Generating a function within a logic design using a dialog box 失效
标题翻译：使用对话框在逻辑设计中生成函数
公开(公告)号：US06708321B2
公开(公告)日：2004-03-16
申请号：US10038706
申请日：2002-01-04
申请人： William R. Wheeler , Mathew J. Adiletta , Timothy J. Fennell
发明人： William R. Wheeler , Mathew J. Adiletta , Timothy J. Fennell
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A method of generating a function within a logic design of a circuit, includes representing the function using an operator. The function has n operands, where n>1. The method also includes presenting the function within a schematic representation of the logic design. Other features may include displaying a dialog box and inputting data that corresponds to the function.
摘要翻译：在电路的逻辑设计中产生功能的方法包括使用操作者来表示功能。该函数具有n个操作数，其中n> 1。该方法还包括在逻辑设计的示意图中呈现功能。其他特征可以包括显示对话框并输入对应于该功能的数据。

54. 发明授权

US06643836B2 Displaying information relating to a logic design 失效
公开(公告)号：US06643836B2
公开(公告)日：2003-11-04
申请号：US09941923
申请日：2001-08-29
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Displaying information relating to a logic design includes generating a first display that relates to the logic design, the first display being associated with other information not included in the first display, retrieving the other information in response to a user input, and generating a second display that relates to the logic design based on the other information.

55. 发明授权

US6052706A Apparatus for performing fast multiplication 失效
标题翻译：用于执行快速乘法的装置
公开(公告)号：US6052706A
公开(公告)日：2000-04-18
申请号：US977732
申请日：1997-11-25
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5338 , G06F7/535 , G06F2207/3884 , G06F2207/5352
摘要： In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process. The foregoing arrangement provides a flexible approach which can be adapted for particular bandwidth requirements and constraints which vary with each particular application and system in which such a process is performed.
摘要翻译：根据本发明，提供了一种用于对数据流执行迭代处理的电路。迭代过程包括对数据流的一部分进行操作以产生作为后级的输入的输出的流水线级。流水线级中的至少一个包括用于在将输出传递到后级之前将来自流水线级的输出作为输入再循环到流水线级预定次数的装置。预定次数表示包括多于一个时钟信号的断言的时钟周期。通过这样的布置，根据特定带宽要求执行诸如乘法和除法的处理的电路比执行相同处理的其它电路中需要的硬件要少。上述布置提供了一种灵活的方法，该方法可以针对特定的带宽要求和约束进行调整，每个特定的应用和系统在执行这种处理的每一个特定的应用和系统中

56. 发明授权

US5995080A Method and apparatus for interleaving and de-interleaving YUV pixel data 失效
标题翻译：用于交织和解交织YUV像素数据的方法和装置
公开(公告)号：US5995080A
公开(公告)日：1999-11-30
申请号：US668199
申请日：1996-06-21
申请人： Larry Louis Biro , Matthew Howard Reilly , Matthew James Adiletta , William R. Wheeler
发明人： Larry Louis Biro , Matthew Howard Reilly , Matthew James Adiletta , William R. Wheeler
IPC分类号： H04N7/26 , H04N7/36 , H04N7/46 , H04N7/50 , G09G5/04
CPC分类号： H04N19/577 , H04N19/126 , H04N19/14 , H04N19/176 , H04N19/177 , H04N19/42 , H04N19/51 , H04N19/61 , H04N19/146 , H04N19/152 , Y10S707/99942
摘要： An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.
摘要翻译：提供了一种用于执行双程实时视频压缩的方法的装置和方法。用软件确定诸如编码和量化值之类的战术决策，而在硬件中执行功能执行步骤。通过适当地分配软件和硬件之间的任务，利用每种类型的处理的优点，同时最小化硬件复杂性和数据传输要求。允许压缩单元实时操作的一个关键概念是架构和流水线均允许B帧被执行无序。通过缓冲B帧，可以执行双遍运动估计技术，以根据帧的要求定制比特使用，从而提供更有吸引力的输出图像。

57. 发明授权

US5948972A Dual stage instrument for scanning a specimen 失效
标题翻译：用于扫描样品的双级仪器
公开(公告)号：US5948972A
公开(公告)日：1999-09-07
申请号：US730641
申请日：1996-10-11
申请人： Amin Samsavar , William R. Wheeler , Steven G. Eaton
发明人： Amin Samsavar , William R. Wheeler , Steven G. Eaton
IPC分类号： G01Q70/06 , G01B3/00 , G01B5/28 , G01B7/34 , G01B21/30 , G01Q10/02 , G01Q10/04 , G01Q20/00 , G01Q60/00 , G01Q90/00 , G12B5/00
CPC分类号： G01Q10/04 , B82Y35/00 , G01B3/008 , G01B7/34 , G01Q10/02 , G01Q30/02 , G01Q70/06 , Y10S977/834 , Y10S977/849 , Y10S977/852 , Y10S977/867 , Y10S977/868 , Y10S977/872 , Y10S977/874
摘要： A dual stage scanning instrument includes a sensor for sensing a parameter of a sample and coarse and fine stages for causing relative motion between the sensor and the sample. The coarse stage has a resolution of about 1 micrometer and the fine stage has a resolution of 1 nanometer or better. The sensor is used to sense the parameter when both stages cause relative motion between the sensor assembly and the sample, The sensor may be used to sense height variations of the sample surface as well as thermal variations electrostatic, magnetic, light reflectivity or light transmission parameters at the same time when height variation is sensed. By performing along scan at a coarser resolution and short scans a high resolution using the same probe tip or two probe tips at fixed relative positions, data obtained from the long and short scans can be correlated accurately.
摘要翻译：双级扫描仪器包括用于感测样品参数的传感器和用于引起传感器和样品之间的相对运动的粗细级和细级级的传感器。粗糙度分辨率约为1微米，细微分辨率为1纳米或更好。传感器用于在两个阶段引起传感器组件和样品之间的相对运动时感测参数。传感器可用于检测样品表面的高度变化以及热变化，静电，磁性，光反射率或光传输参数同时感测到高度变化。通过以更粗糙的分辨率执行扫描，并且在固定的相对位置使用相同的探针尖端或两个探针尖端短扫描高分辨率，可以精确地相关联从长扫描和短扫描得到的数据。

58. 发明授权

US5353424A Fast tag compare and bank select in set associative cache 失效
标题翻译：快速标签比较和集合相关缓存中的存储区选择
公开(公告)号：US5353424A
公开(公告)日：1994-10-04
申请号：US794865
申请日：1991-11-19
申请人： Hamid Partovi , William R. Wheeler , Michael Leary , Michael A. Case , Steven Butler , Rajesh Khanna
发明人： Hamid Partovi , William R. Wheeler , Michael Leary , Michael A. Case , Steven Butler , Rajesh Khanna
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864
摘要： A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.
摘要翻译：用于计算机系统中的组相关高速缓存的标签比较器和存储体选择器在最小时间内操作，使得在存储器周期中早期产生高速缓存命中或未命中信号。高速缓存的数据存储器具有两个（或更多个）存储体，每个存储体具有标签存储，并且当标签转换正在进行时，使用索引（低位地址位）分开存取和并行访问两个存储体。执行两个逐位标签比较，每个标签存储一个，产生两个多位匹配指示，每个标签存储中每个标签位一位。这两个匹配指示被应用于两个单独的动态NOR门，并且两个输出被施加到逻辑电路以检测命中并产生一个存储体选择输出。比较操作有四个可能的结果：两家银行错失，左岸点击，右岸点击，两家银行都受到打击。后面的条件表示可能的模糊性，并且都不应该使用数据项，所以发出了错误信号。使用流通设计，比较器在很大程度上是自定时的，与时钟边沿不同。银行选择逻辑中的延迟元素允许银行彼此定时，并且采用电流限制器来均衡缺失信号的定时，而不管匹配线的数量如何切换高（这取决于数据）。产生20位20位匹配位的地址将导致与不产生不匹配位的地址大致相同的定时的或非门输出，即使前者将仅接通一个晶体管来放电NOR门的预充电输出节点，而后来将打开二十条出路。尽管本文中示出了双向组关联高速缓存作为示例实施例，但是本发明的特征之一是更高级别的关联性，例如四路和八路同样适应。

59. 发明授权

US5019967A Pipeline bubble compression in a computer system 失效
标题翻译：在计算机系统中管道气泡压缩
公开(公告)号：US5019967A
公开(公告)日：1991-05-28
申请号：US221988
申请日：1988-07-20
申请人： William R. Wheeler , George M. Uhler
发明人： William R. Wheeler , George M. Uhler
IPC分类号： G06F9/38
CPC分类号： G06F9/3873 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3867
摘要： Bubble compression in a pipelined central processing unit (CPU) of a computer system is provided. A bubble represents a stage in the pipeline that cannot perform any useful work due to the lack of data from an earlier pipeline stage. When a particular pipeline stage has stalled, the CPU instructions that have already passed through the stage continue to move ahead and leave behind vacant stages or bubbles. If a bubble is introduced into a pipeline and the pipeline subsequently stalls, the disclosed CPU takes advantage of this stalled condition to compress the previously introduced bubble.

60. 发明授权

US4376482A Wafer orientation system 失效
标题翻译：晶圆定向系统
公开(公告)号：US4376482A
公开(公告)日：1983-03-15
申请号：US265412
申请日：1981-05-19
申请人： William R. Wheeler , George J. Kren , David D. Clementson
发明人： William R. Wheeler , George J. Kren , David D. Clementson
IPC分类号： B65G47/244 , H01L21/68 , B65G47/24
CPC分类号： H01L21/68 , B65G47/244
摘要： A wafer orienting apparatus having inwardly biased rollers, spaced about the circumferential edge of a wafer in contact with the edge. Two of the rollers are spaced apart a distance less than the dimension of a primary flat registration edge and are mounted to follow the wafer edge upon rotation of the wafer. When a flat registration edge passes these closely spaced rollers they move inwardly, activating switches associated with a coincidence circuit. When both switches are simultaneously activated, the coincidence circuit produces a signal which stops wafer rotation, thereby orienting the wafer. The rollers are mounted so that they can be moved from the path of wafer travel after wafer orientation, permitting a queue of wafers to be oriented, one after the other.
摘要翻译：具有向内偏压的辊的晶片定向装置，其间隔开与所述边缘接触的晶片的周边边缘。两个辊间隔开一个小于主平面配准边缘的尺寸的距离，并且在晶片旋转时安装成跟随晶片边缘。当平面配准边缘通过这些紧密间隔的辊时，它们向内移动，启动与重合电路相关联的开关。当两个开关同时被激活时，符合电路产生停止晶片旋转的信号，从而使晶片定向。辊子被安装成使得它们可以在晶片取向之后从晶片移动的路径移动，从而允许晶片排队一个接一个地定向。

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