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51. 发明申请

US20120261753A1 DMOS Transistor with a Slanted Super Junction Drift Structure 有权
标题翻译：具有倾斜超结结漂移结构的DMOS晶体管
公开(公告)号：US20120261753A1
公开(公告)日：2012-10-18
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, JR. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

52. 发明申请

US20120154956A1 Self protected snapback device driven by driver circuitry using high side pull-up avalanche diode 审中-公开
标题翻译：使用高侧上拉雪崩二极管的驱动电路驱动的自保护快速恢复装置
公开(公告)号：US20120154956A1
公开(公告)日：2012-06-21
申请号：US12928714
申请日：2010-12-17
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H02H7/00
CPC分类号： H01L27/0255 , H01L27/0285 , H01L29/7817 , H01L29/7821 , H02H9/046 , H03K17/0822 , H03K17/122
摘要： In a power device such as an NLDMOS power array comprising multiple NLDMOS devices, the gates of which are driven by a driver, self protection against overvoltage events is implemented by providing a high side pull-up avalanche diode connected to at least some of the gates of the NLDMOS devices.
摘要翻译：在诸如包括多个NLDMOS器件的NLDMOS功率阵列的功率器件中，其门由驱动器驱动，通过提供连接到至少一些栅极的高侧上拉雪崩二极管实现过压事件的自我保护的NLDMOS设备。

53. 发明授权

US07754540B2 Method of forming a SiGe DIAC ESD protection structure 有权
标题翻译：形成SiGe DIAC ESD保护结构的方法
公开(公告)号：US07754540B2
公开(公告)日：2010-07-13
申请号：US12395506
申请日：2009-02-27
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L21/332
CPC分类号： H01L27/0259
摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.
摘要翻译：用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

54. 发明授权

US07754505B1 Method of forming a silicon-based light-emitting structure 有权
标题翻译：形成硅基发光结构的方法
公开(公告)号：US07754505B1
公开(公告)日：2010-07-13
申请号：US12284290
申请日：2008-09-19
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
IPC分类号： H01L21/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译：形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

55. 发明授权

US07705403B1 Programmable ESD protection structure 有权
标题翻译：可编程ESD保护结构
公开(公告)号：US07705403B1
公开(公告)日：2010-04-27
申请号：US11324455
申请日：2006-01-03
申请人： Vladislav Vashchenko , Yuri Mirgorodski , Peter J. Hopper
发明人： Vladislav Vashchenko , Yuri Mirgorodski , Peter J. Hopper
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/87
摘要： In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.
摘要翻译：在LVTSCR或快速恢复型NMOS ESD结构中，通过引入与ESD结构的控制栅极电容耦合的浮动栅极，并根据需要对浮动栅极进行编程，从而提供低电压保护以及更高的电压保护。

56. 发明授权

US07528012B1 Method for forming heat sinks on silicon on insulator wafers 有权
标题翻译：在绝缘体硅片上形成散热片的方法
公开(公告)号：US07528012B1
公开(公告)日：2009-05-05
申请号：US11508495
申请日：2006-08-22
申请人： Peter J. Hopper , Iouri Mirgorodski , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Iouri Mirgorodski , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L21/00
CPC分类号： H01L29/78606 , H01L23/3677 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.
摘要翻译：散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。该装置包括形成在晶片的有源硅层中的晶体管。活性表面形成在氧化物层和体硅层上。在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。塞子延伸穿过本体层的厚度到氧化物层。此后，塞子填充有导热材料，例如金属或DAG（导热浆）。在运行期间，来自晶体管的热量通过散热器消散。在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。

57. 发明授权

US07462874B1 Silicon-based light-emitting structure 有权
标题翻译：硅基发光结构
公开(公告)号：US07462874B1
公开(公告)日：2008-12-09
申请号：US11403516
申请日：2006-04-13
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
IPC分类号： H01L33/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译：形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

58. 发明授权

US07422952B1 Method of forming a BJT with ESD self protection 有权
标题翻译：用ESD自我保护形成BJT的方法
公开(公告)号：US07422952B1
公开(公告)日：2008-09-09
申请号：US11799954
申请日：2007-05-03
申请人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0821
摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
摘要翻译：将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。

59. 发明授权

US07375579B1 Programming of fuse-based memories using snapback devices 有权
标题翻译：使用快速恢复器件编程基于熔丝的存储器
公开(公告)号：US07375579B1
公开(公告)日：2008-05-20
申请号：US11198796
申请日：2005-08-04
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： H01H37/76
CPC分类号： G11C17/16 , G11C17/18
摘要： In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.
摘要翻译：在基于熔丝的可编程电路块中，通过使用与多熔丝串联连接的快速恢复装置将多晶硅熔断器烧掉。

60. 发明授权

US07375393B1 Non-volatile memory (NVM) retention improvement utilizing protective electrical shield 有权
公开(公告)号：US07375393B1
公开(公告)日：2008-05-20
申请号：US11044511
申请日：2005-01-27
申请人： Yuri Mirgorodski , Peter J. Hopper , Vladislav Vashchenko
发明人： Yuri Mirgorodski , Peter J. Hopper , Vladislav Vashchenko
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/42324
摘要： An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

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