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51. 发明申请

US20140093068A1 INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 有权
标题翻译： 128位处理器的SKEIN256 SHA3算法指令集
公开(公告)号：US20140093068A1
公开(公告)日：2014-04-03
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

52. 发明申请

US20170091120A1 Securing Writes to Memory Modules Having Memory Controllers 审中-公开
公开(公告)号：US20170091120A1
公开(公告)日：2017-03-30
申请号：US14865675
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/14 , G06F11/16 , G06F11/32
CPC分类号： G06F12/1408 , G06F11/1608 , G06F11/327 , G06F13/00 , G06F21/575 , G06F21/79 , G06F2212/1052
摘要： A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.

53. 发明申请

US20140189368A1 INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY 有权
标题翻译：指示和逻辑提供SIMD安全冲击圆形功能
公开(公告)号：US20140189368A1
公开(公告)日：2014-07-03
申请号：US13731004
申请日：2012-12-29
申请人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
发明人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
IPC分类号： G06F21/60
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G06F15/8007 , G06F21/602 , G06F21/64
摘要： Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.
摘要翻译：说明和逻辑提供SIMD安全散列圆切片功能。一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分圆周运算，旋转设定部分旋转设定。处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

54. 发明申请

US20170093823A1 Encrypting Observable Address Information 审中-公开
公开(公告)号：US20170093823A1
公开(公告)日：2017-03-30
申请号：US14865751
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： H04L29/06 , G06F12/14
CPC分类号： H04L63/061 , G06F12/1416 , G06F21/78 , G06F2212/1052 , H04L63/0442
摘要： Address information may be secured by sharing a key between a host central processing unit subsystem and an external memory. Information about how write addresses are modified may be exchanged between said subsystem and said memory. The write addresses for the same memory location are changed each time a write accesses the address.

55. 发明申请

US20170180116A1 END-TO-END PROTECTION SCHEME INVOLVING ENCRYPTED MEMORY AND STORAGE 审中-公开
公开(公告)号：US20170180116A1
公开(公告)日：2017-06-22
申请号：US14979349
申请日：2015-12-22
申请人： Kirk S. Yap , Vinodh Gopal
发明人： Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/06 , G09C1/00
CPC分类号： H04L9/065 , G09C1/00 , H04L2209/12
摘要： Systems, apparatuses and methods may provide for generating encrypted data based on write data received at a first data input of an apparatus and generating an inbound protection bit stream based on the write data. Additionally, write protection metadata may be generated based on the inbound protection bit stream and a first counter. In one example, decrypted data may also be generated based on read data received at a second data input of the apparatus. In such a case, a first outbound protection bit stream may be generated based on the decrypted data, and a second outbound protection bit stream may be generated based on a second counter and outbound protection metadata. Moreover, an error signal may be generated in response to a difference between the first outbound protection bit stream and the second outbound protection bit stream.

56. 发明申请

US20190042496A1 DELAYED LINK COMPRESSION SCHEME 审中-公开
公开(公告)号：US20190042496A1
公开(公告)日：2019-02-07
申请号：US16140472
申请日：2018-09-24
申请人： Simon N. Peffers , Kirk S. Yap , Sean Gulley , Vinodh Gopal , Wajdi Feghali
发明人： Simon N. Peffers , Kirk S. Yap , Sean Gulley , Vinodh Gopal , Wajdi Feghali
IPC分类号： G06F13/16 , H04L29/06 , G06F13/28 , G06F13/40
摘要： Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.

57. 发明申请

US20090141887A1 METHOD AND APPARATUS FOR GENERIC MULTI-STAGE NESTED HASH PROCESSING 失效
标题翻译：用于通用多级嵌入式处理的方法和装置
公开(公告)号：US20090141887A1
公开(公告)日：2009-06-04
申请号：US11949767
申请日：2007-12-03
申请人： Kirk S. Yap , Stephanie L. Hirnak , Daniel G. Borkowski
发明人： Kirk S. Yap , Stephanie L. Hirnak , Daniel G. Borkowski
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , H04L63/12 , H04L2209/125 , H04L2209/20 , H04L2209/38
摘要： A generic multi-stage nested hash unit that provides support for generic, multi-stage nested hashes accelerates a wide range of security algorithms and protocols. The supported security algorithms and protocols include SSL v3 MAC, TLS PRF, and SSL v3 Key Material Generation. The hash unit allows the same code to be used to generate the MAC even when the MAC algorithms are different, for example, for SSL and TLS protocols.
摘要翻译：通用的多阶嵌套散列单元提供对通用多级嵌套散列的支持，可加速各种安全算法和协议。支持的安全算法和协议包括SSL v3 MAC，TLS PRF和SSL v3密钥生成。散列单元允许使用相同的代码来生成MAC，即使MAC算法不同，例如对于SSL和TLS协议也是如此。

58. 发明申请

US20160182223A1 Encryption Interface 有权
标题翻译：加密界面
公开(公告)号：US20160182223A1
公开(公告)日：2016-06-23
申请号：US14581946
申请日：2014-12-23
申请人： Eugene M. Kishinevsky , Uday R. Savagaonkar , Alpa T. Narendra Trivedi , Siddhartha Chhabra , Baiju V. Patel , Men Long , Kirk S. Yap , David M. Durham
发明人： Eugene M. Kishinevsky , Uday R. Savagaonkar , Alpa T. Narendra Trivedi , Siddhartha Chhabra , Baiju V. Patel , Men Long , Kirk S. Yap , David M. Durham
IPC分类号： H04L9/06 , G06F12/14 , G06F21/62
CPC分类号： H04L9/0631 , G06F12/1408 , G06F12/1425 , G06F21/602 , G06F21/85 , G06F2212/1052 , G06F2212/402 , G09C1/00 , H04L2209/125 , Y02D10/13
摘要： Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.
摘要翻译：描述加密接口技术。处理器可以包括系统代理，加密接口和存储器控制器。系统代理可以与硬件功能块通信数据。加密接口可以耦合在系统代理和存储器控制器之间。加密接口可以从系统代理接收明文请求，加密明文请求以获得加密请求，并将加密的请求传送到存储器控制器。存储器控制器可以将加密的请求传送到计算设备的主存储器。

59. 发明申请

US20150089245A1 DATA STORAGE IN PERSISTENT MEMORY 审中-公开
标题翻译：数据存储在存储器中
公开(公告)号：US20150089245A1
公开(公告)日：2015-03-26
申请号：US14038295
申请日：2013-09-26
申请人： Asher M. Altman , Kirk S. Yap , Raj K. Ramanujan
发明人： Asher M. Altman , Kirk S. Yap , Raj K. Ramanujan
IPC分类号： G06F12/14 , G06F21/60
CPC分类号： G06F12/1408 , G06F21/602 , G06F21/79 , G06F2212/1052 , G06F2221/2143
摘要： Embodiments include systems, methods, and apparatuses associated with storing data in a persistent memory are disclosed herein. In embodiments, a memory controller may be configured to encrypt data with an encryption key, and the encrypted data may be stored in persistent memory. The memory controller may be further configured to alter and/or destroy the encryption key in response to a reset event. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开的实施例包括与在永久存储器中存储数据相关联的系统，方法和装置。在实施例中，存储器控制器可以被配置为用加密密钥加密数据，并且加密的数据可以被存储在持久存储器中。存储器控制器可以被进一步配置为响应于重置事件而改变和/或销毁加密密钥。可以公开和/或要求保护其他实施例。

60. 发明授权

US08363827B2 Method and apparatus for generic multi-stage nested hash processing 失效
标题翻译：通用多级嵌套散列处理方法和装置
公开(公告)号：US08363827B2
公开(公告)日：2013-01-29
申请号：US11949767
申请日：2007-12-03
申请人： Kirk S. Yap , Stephanie L. Hirnak , Daniel G. Borkowski
发明人： Kirk S. Yap , Stephanie L. Hirnak , Daniel G. Borkowski
IPC分类号： H04K1/00
CPC分类号： H04L9/0643 , H04L63/12 , H04L2209/125 , H04L2209/20 , H04L2209/38
摘要： A generic multi-stage nested hash unit that provides support for generic, multi-stage nested hashes accelerates a wide range of security algorithms and protocols. The supported security algorithms and protocols include SSL v3 MAC, TLS PRF, and SSL v3 Key Material Generation. The hash unit allows the same code to be used to generate the MAC even when the MAC algorithms are different, for example, for SSL and TLS protocols.
摘要翻译：通用的多阶嵌套散列单元提供对通用多级嵌套散列的支持，可加速各种安全算法和协议。支持的安全算法和协议包括SSL v3 MAC，TLS PRF和SSL v3密钥生成。散列单元允许使用相同的代码来生成MAC，即使MAC算法不同，例如对于SSL和TLS协议也是如此。

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