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51. 发明申请

US20090010077A1 SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL 有权
标题翻译：具有嵌入式动态随机存取存储器扫描的移位寄存器
公开(公告)号：US20090010077A1
公开(公告)日：2009-01-08
申请号：US11772592
申请日：2007-07-02
申请人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
发明人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
IPC分类号： G11C7/00
CPC分类号： G11C19/184 , G11C11/41 , G11C14/00 , G11C29/32 , G11C2029/3202
摘要： A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
摘要翻译：混合移位寄存器锁存器，其使用用于系统操作的静态存储器单元和仅用于测试操作的动态存储器单元。在阵列单元中设置L1存储元件和L2存储元件。 L1存储元件包括静态随机存取存储单元。 L1存储元件在阵列单元的系统和测试操作期间使用。 L2存储元件包括动态随机存取存储单元。 L2存储元件仅在阵列单元的测试操作期间使用。

52. 发明授权

US07474574B1 Shift register latch with embedded dynamic random access memory scan only cell 有权
标题翻译：移位寄存器锁存器与嵌入式动态随机存取存储器扫描单元格
公开(公告)号：US07474574B1
公开(公告)日：2009-01-06
申请号：US11772592
申请日：2007-07-02
申请人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
发明人： Vikas Agarwal , Sam Gat-Shang Chu , Saiful Islam , Philip George Shephard, III
IPC分类号： G11C7/00
CPC分类号： G11C19/184 , G11C11/41 , G11C14/00 , G11C29/32 , G11C2029/3202
摘要： A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
摘要翻译：混合移位寄存器锁存器，其使用用于系统操作的静态存储器单元和仅用于测试操作的动态存储器单元。在阵列单元中设置L1存储元件和L2存储元件。 L1存储元件包括静态随机存取存储单元。 L1存储元件在阵列单元的系统和测试操作期间使用。 L2存储元件包括动态随机存取存储单元。 L2存储元件仅在阵列单元的测试操作期间使用。

53. 发明授权

US07424691B2 Method for verifying performance of an array by simulating operation of edge cells in a full array model 有权
标题翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的方法
公开(公告)号：US07424691B2
公开(公告)日：2008-09-09
申请号：US11279312
申请日：2006-04-11
申请人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
发明人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
IPC分类号： G06F17/50 , G11C29/00
CPC分类号： G06F17/5022
摘要： A method for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的方法减少了完整设计验证所需的计算时间。阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。观察到字线到达以确定最坏情况行进行选择。对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

54. 发明申请

US20080189535A1 Method and System for Dependency Tracking and Flush Recovery for an Out-Of-Order Microprocessor 失效
标题翻译：用于无序微处理器的依赖跟踪和冲洗恢复的方法和系统
公开(公告)号：US20080189535A1
公开(公告)日：2008-08-07
申请号：US11669999
申请日：2007-02-01
申请人： Vikas Agarwal , William E. Burky , Krishnan Kailas , Balaram Sinharoy
发明人： Vikas Agarwal , William E. Burky , Krishnan Kailas , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3863
摘要： A method for dependency tracking and flush recovery for an out-of-order processor includes recording, in a last definition (DEF) data structure, an identifier of a first instruction as the most recent instruction in an instruction sequence that defines contents of the particular logical register and recording, in a next DEF data structure, the identifier of the first instruction in association with an identifier of a previous second instruction also indicating an update to the particular logical register. In addition, a recovery array is updated to indicate which of the instructions in the instruction sequence updates each of the plurality of logical registers. In response to misspeculation during execution of the instruction sequence, the processor performs a recovery operation to place the identifier of the second instruction in the last DEF data structure by reference to the next DEF data structure and the recovery array.
摘要翻译：用于无序处理器的依赖性跟踪和刷新恢复的方法包括在最后定义（DEF）数据结构中记录第一指令的标识符作为指定序列中的最新指令，其定义特定的内容在下一个DEF数据结构中，逻辑寄存器和记录与第一指令的标识符相关联，该标识符还指示特定逻辑寄存器的更新。此外，更新恢复阵列以指示指令序列中的哪些指令更新多个逻辑寄存器中的每一个。响应于执行指令序列期间的错误，处理器执行恢复操作，以通过参考下一个DEF数据结构和恢复阵列将第二指令的标识符放置在最后的DEF数据结构中。

55. 发明申请

US20080131508A1 Oral transmucosal nicotine dosage form 审中-公开
标题翻译：口服经粘膜尼古丁剂型
公开(公告)号：US20080131508A1
公开(公告)日：2008-06-05
申请号：US11986097
申请日：2007-11-20
申请人： Vikas Agarwal , Brian I. Hague , Rajendra K. Khankari
发明人： Vikas Agarwal , Brian I. Hague , Rajendra K. Khankari
IPC分类号： A61K9/46 , A61K31/465 , A61P25/30
CPC分类号： A61K31/465 , A61K9/0007 , A61K9/0056
摘要： The invention described herein relates to an oral transmucosal solid dosage form useful in treating nicotine addiction or as a nicotine substitute or replacement. By virtue of the formulation in combination with nicotine, the invention transmucosally delivers an effective amount of nicotine to the recipient while permitting the accomplishing of such, and manufacture of such, using a relatively small, convenient and orally comfortable dosage form (e.g., tablet) size.
摘要翻译：本文描述的本发明涉及可用于治疗尼古丁成瘾或作为尼古丁替代物或替代物的口腔粘膜固体剂型。由于与尼古丁组合的制剂，本发明将有效量的尼古丁透析递送至受体，同时允许使用相对较小，方便和口服舒适的剂型（例如片剂）来实现和制造，尺寸。

56. 发明申请

US20080123437A1 Apparatus for Floating Bitlines in Static Random Access Memory Arrays 审中-公开
标题翻译：静态随机存取存储器阵列中浮动位线的装置
公开(公告)号：US20080123437A1
公开(公告)日：2008-05-29
申请号：US11564697
申请日：2006-11-29
申请人： Vikas Agarwal , Sam G. Chu , Jose A. Paredes
发明人： Vikas Agarwal , Sam G. Chu , Jose A. Paredes
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/1012 , G11C7/1051 , G11C7/18 , G11C11/413
摘要： An apparatus for floating read bitlines of a static random access memory (SRAM) is disclosed. The SRAM includes a first and second SRAM cell columns, a first and second read bitlines, and a multiplexor. The multiplexor is coupled to the first and second SRAM cell columns via the first and second read bitlines, respectively. The multiplexor is capable of selectively transmitting data from the first or second SRAM cell column via the first or second read bitline, respectively, to an output. In addition, the multiplexor allows the first read bitline and/or the second read bitline to remain uncharged when no data are being read from the first SRAM cell column and/or the second SRAM cell column.
摘要翻译：公开了一种用于浮动读取静态随机存取存储器（SRAM）的位线的装置。 SRAM包括第一和第二SRAM单元列，第一和第二读位线以及多路复用器。多路复用器分别经由第一和第二读取位线耦合到第一和第二SRAM单元列。复用器能够分别经由第一或第二读取位线从第一或第二SRAM单元列选择性地发送数据到输出。此外，当没有从第一SRAM单元列和/或第二SRAM单元列读取数据时，多路复用器允许第一读取位线和/或第二读取位线保持不带电。

57. 发明授权

US07174379B2 Managing server resources for hosted applications 失效
标题翻译：管理托管应用程序的服务器资源
公开(公告)号：US07174379B2
公开(公告)日：2007-02-06
申请号：US09921868
申请日：2001-08-03
申请人： Vikas Agarwal , Girish Chafle , Neeran Mohan Karnik , Arun Kumar , Ashish Kundu , Johara Shahabuddin , Pradeep Varma
发明人： Vikas Agarwal , Girish Chafle , Neeran Mohan Karnik , Arun Kumar , Ashish Kundu , Johara Shahabuddin , Pradeep Varma
IPC分类号： G06F15/173 , G06F9/445
CPC分类号： G06F9/505 , G06F9/5055 , H04L67/20 , H04L67/22 , H04L69/329
摘要： In an ASP server farm, requests to use an application are directed to a particular executing instance of the application (or an appropriate component thereof) that is identified as being the least loaded of the available such instances of the application or its component. The number of such instances is dynamically increased or decreased in response to the number of requests for the application or components thereof. Requests may be directed (in accordance with the first aspect) or the instances adjusted (in accordance with a second aspect) on a per client-basis, in which instances of the application and/or components thereof are reserved for the use of a user or a particular group of users. Operation in this manner facilitates compliance with service agreements with respective users or groups of users.
摘要翻译：在ASP服务器场中，使用应用程序的请求被引导到应用程序的特定执行实例（或其适当的组件），该实例被标识为应用程序或其组件的可用这样的实例的最少加载。响应于应用程序的请求数量或其组件的数量，这种实例的数量被动态地增加或减少。请求可以针对每个客户端（根据第一方面）或被调整（根据第二方面）的实例，其中应用和/或其组件的实例被保留用于使用用户或特定的一组用户。以这种方式进行操作便于遵守与各个用户或用户组的服务协议。

58. 发明申请

US20050142198A1 Effervescent oral fentanyl dosage form and methods of administering fentanyl 有权
标题翻译：泡腾口服芬太尼剂型及施用芬太尼的方法
公开(公告)号：US20050142198A1
公开(公告)日：2005-06-30
申请号：US11027353
申请日：2004-12-30
申请人： Derek Moe , Vikas Agarwal , Walid Habib
发明人： Derek Moe , Vikas Agarwal , Walid Habib
IPC分类号： A61K9/00 , A61K9/20 , A61K9/46 , A61K31/445 , A61K9/70
CPC分类号： A61K31/445 , A61K9/0007 , A61K9/006 , A61K9/205
摘要： Fentanyl-containing dosage forms and methods using same are described. These dosage forms include substantially less fentanyl by weight than known oral formulation and have advantages in terms of reduced cost and reduced side effects. These dosage forms are intended for oral administration of fentanyl across the oral mucosa.
摘要翻译：描述了含有芬太尼的剂型及使用它们的方法。这些剂型包括比已知口服制剂重量少的芬太尼，并且在降低成本和减少副作用方面具有优点。这些剂型旨在口服口服粘膜上的芬太尼。

59. 发明授权

US08356267B2 Statistical method for hierarchically routing layout utilizing flat route information 有权
标题翻译：使用平面路由信息分层布线布局的统计方法
公开(公告)号：US08356267B2
公开(公告)日：2013-01-15
申请号：US12912819
申请日：2010-10-27
申请人： Vikas Agarwal , Yonatan Mittlefehldt , Jafar Nahidi
发明人： Vikas Agarwal , Yonatan Mittlefehldt , Jafar Nahidi
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An integrated circuit design is routed by first creating temporary routes in a flattened layout, generating blockage information for sub-blocks in the layout based on the temporary routes, and establishing a routing order for cells using a depth-first search. Cells in the original layout are then routed according to the routing order using the blockage information. The temporary routes are sorted into internal routes, terminal routes, and spanning routes. Blockage information for each sub-block includes a first cellview equal to the internal routes, a second cellview equal to the terminal routes plus the spanning routes, and a third cellview equal to the total tracks in the sub-block minus the first and second cellviews. The invention is particularly suited for routing a hierarchical integrated circuit design. By examining the complete hierarchy, the invention ensures that enough metal will be remaining at upper level sub-blocks to complete the routing automatically.
摘要翻译：通过首先在平坦化布局中创建临时路由来路由集成电路设计，基于临时路由生成布局中的子块的阻塞信息，以及使用深度优先搜索来建立小区的路由顺序。然后使用阻塞信息，根据路由顺序路由原始布局中的单元。临时路由分为内部路由，终端路由和跨越路由。每个子块的阻塞信息包括等于内部路由的第一小区视图，等于终端路由加上跨越路由的第二小区视图，以及等于子块中的总轨迹的第三小区视图减去第一和第二小区视图。本发明特别适用于布线分级集成电路设计。通过检查完整的层次结构，本发明确保在上级子块中剩余足够的金属以自动完成路由。

60. 发明申请

US20120110536A1 STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION 有权
标题翻译：使用平坦路径信息进行层次分层布局的统计方法
公开(公告)号：US20120110536A1
公开(公告)日：2012-05-03
申请号：US12912819
申请日：2010-10-27
申请人： Vikas Agarwal , Yonatan Mittlefehldt , Jafar Nahidi
发明人： Vikas Agarwal , Yonatan Mittlefehldt , Jafar Nahidi
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An integrated circuit design is routed by first creating temporary routes in a flattened layout, generating blockage information for sub-blocks in the layout based on the temporary routes, and establishing a routing order for cells using a depth-first search. Cells in the original layout are then routed according to the routing order using the blockage information. The temporary routes are sorted into internal routes, terminal routes, and spanning routes. Blockage information for each sub-block includes a first cellview equal to the internal routes, a second cellview equal to the terminal routes plus the spanning routes, and a third cellview equal to the total tracks in the sub-block minus the first and second cellviews. The invention is particularly suited for routing a hierarchical integrated circuit design. By examining the complete hierarchy, the invention ensures that enough metal will be remaining at upper level sub-blocks to complete the routing automatically.
摘要翻译：通过首先在平坦化布局中创建临时路由来路由集成电路设计，基于临时路由生成布局中的子块的阻塞信息，以及使用深度优先搜索来建立小区的路由顺序。然后使用阻塞信息，根据路由顺序路由原始布局中的单元。临时路由分为内部路由，终端路由和跨越路由。每个子块的阻塞信息包括等于内部路由的第一小区视图，等于终端路由加上跨越路由的第二小区视图，以及等于子块中的总轨迹的第三小区视图减去第一和第二小区视图。本发明特别适用于布线分级集成电路设计。通过检查完整的层次结构，本发明确保在上级子块中剩余足够的金属以自动完成路由。

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