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51. 发明授权

US5905717A Echo canceller for a packet signal 失效
标题翻译：用于分组信号的回波消除器
公开(公告)号：US5905717A
公开(公告)日：1999-05-18
申请号：US757411
申请日：1996-11-27
申请人： Atsushi Hasegawa
发明人： Atsushi Hasegawa
IPC分类号： H03H21/00 , H03H17/00 , H04B3/23 , H04L5/14
CPC分类号： H04B3/23
摘要： An echo canceller of the present invention and for packet signals includes a buffer (4) for converting the rate of a residual echo, and a buffer (1) for converting the rate of a received packet. An echo path estimator (2) generates, by referencing the outputs of the buffers (1, 4), filter coefficients for estimating an echo path. An adaptive FIR (Finite Impulse Response) filter (3) performs convolutional computation with the filter coefficients and the output of the buffer (1) for thereby outputting a false echo component. A buffer (5) packetizes the false echo component. A subtracter (6) subtracts the packetized false echo component from a packet to be transmitted so as to cancel an echo. Because a line assigned to the packet to be transmitted involves only subtraction, the echo canceller prevents packets from being delayed.
摘要翻译：本发明的回波消除器和分组信号包括用于转换残余回声的速率的缓冲器（4）和用于转换接收到的分组的速率的缓冲器（1）。回波路径估计器（2）通过参考缓冲器（1,4）的输出，生成用于估计回波路径的滤波器系数。自适应FIR（有限脉冲响应）滤波器（3）利用滤波器系数和缓冲器（1）的输出执行卷积运算，从而输出假回波分量。缓冲器（5）打包假回波分量。减法器（6）从要发送的分组中减去打包的假回波分量，以消除回波。由于分配给要发送的数据包的行仅涉及减法，因此回波消除器可防止数据包被延迟。

52. 发明授权

US5822761A Data processing system which controls operation of cache memory based and the address being accessed 失效
标题翻译：控制高速缓存存储器的操作的数据处理系统和被访问的地址
公开(公告)号：US5822761A
公开(公告)日：1998-10-13
申请号：US795639
申请日：1997-02-06
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Masaru Matsumura
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Masaru Matsumura
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F12/0888
摘要： A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.
摘要翻译：在诸如I / O映射微机系统的系统中提供检测电路，以便检测由中央处理单元（CPU）生成的读取访问请求的访问地址是否用于一部分（诸如状态在由中央处理系统可访问的整个存储区域（诸如主存储器和状态寄存器）内的另一个处理设备（诸如I / O设备）可访问的上述微机系统中。如果在高速缓冲存储器中没有找到要由中央处理单元执行的指令取出的数据，则从整个存储区域取出数据。提供了一种写入电路，当检测电路显示存取地址不能由整个存储区域内的其他处理设备访问的部分时，将读取的数据写入高速缓冲存储器，但是写入电路不写入读取的数据数据进入缓存内存。

53. 发明授权

US5148526A Data processing system with an enhanced cache memory control 失效
标题翻译：具有增强的高速缓存存储器控制的数据处理系统
公开(公告)号：US5148526A
公开(公告)日：1992-09-15
申请号：US183401
申请日：1988-04-08
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Masaru Matsumura
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Masaru Matsumura
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F12/0888
摘要： A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned microcomputer system) which is accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) which is accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address does not correspond to the area accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.
摘要翻译：在诸如I / O映射微机系统的系统中提供检测电路，以便检测由中央处理单元（CPU）生成的读取访问请求的访问地址是否对应于区域（例如，在诸如I / O设备的其他处理设备可访问的上述微计算机系统中登记），该处理设备可以由中央处理系统访问的整个存储区域（诸如主存储器和状态寄存器）中。如果在高速缓冲存储器中没有找到要由中央处理单元执行的指令取出的数据，则从整个存储区域取出数据。提供一种写入电路，当检测电路显示存取地址与整个存储区域内的其他处理设备可访问的区域不对应时，读取的数据写入高速缓冲存储器，但是写入电路不写入将数据读取到高速缓冲存储器中。

54. 发明授权

US4926321A Method of searching a queue in response to a search instruction 失效
标题翻译：响应于搜索指令搜索队列的方法
公开(公告)号：US4926321A
公开(公告)日：1990-05-15
申请号：US089818
申请日：1987-08-27
申请人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
发明人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
IPC分类号： G06F9/46 , G06F9/30 , G06F9/312 , G06F17/30
CPC分类号： G06F9/30043 , G06F17/30958 , Y10S707/99933
摘要： A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.
摘要翻译：一种用于搜索数据处理装置的存储器的方法，该数据处理装置包括用于解码指令内容的解码器和用于基于来自解码器的输出执行该指令的执行单元，该方法响应于识别期望数据存储器的搜索指令包括阵列数据结构的存储器中的多个数据存储区域。

55. 发明授权

US4912635A System for reexecuting branch instruction without fetching by storing target instruction control information 失效
标题翻译：用于通过存储目标指令控制信息重新执行分支指令而不进行提取的系统
公开(公告)号：US4912635A
公开(公告)日：1990-03-27
申请号：US151276
申请日：1988-02-01
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Yoshifumi Takamoto
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Yoshifumi Takamoto
IPC分类号： G06F9/38
CPC分类号： G06F9/3846
摘要： The present invention relates to a pipeline data processing apparatus wherein an instruction is fetched from a main storage, the instruction is decoded to generate control information for executing the instruction, and the control information is transferred to an instruction execute circuit. The target address of a branch instruction is stored in the index field of an associative memory, and control information obtained by decoding a target instruction of branch corresponding to the branch instruction is stored in the data field of the associative memory beforehand. When executing the branch instruction, the associative memory is accessed with the target address, and the control information of the corresponding entry is read out and is transferred to the instruction execute circuit, whereupon the instruction execute circuit starts executing the target instruction of branch instruction in succeession to the execution of the branch instruction.
摘要翻译：本发明涉及一种流水线数据处理装置，其中从主存储器取出指令，解码指令以产生用于执行指令的控制信息，并将控制信息传送到指令执行电路。分支指令的目标地址被存储在关联存储器的索引字段中，并且通过解码与分支指令相对应的分支的目标指令获得的控制信息被预先存储在关联存储器的数据字段中。当执行分支指令时，利用目标地址访问关联存储器，读出对应条目的控制信息并将其传送到指令执行电路，由此指令执行电路开始执行分支指令的目标指令成功执行分支指令。

56. 发明授权

US08643636B2 Active matrix display device 有权
公开(公告)号：US08643636B2
公开(公告)日：2014-02-04
申请号：US13723848
申请日：2012-12-21
申请人： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masashiro Maki , Kazutaka Goto
发明人： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masashiro Maki , Kazutaka Goto
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
摘要： A driving circuit for driving a display panel includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

57. 发明授权

US08377765B2 Manufacturing method of liquid crystal display device 有权
标题翻译：液晶显示装置的制造方法
公开(公告)号：US08377765B2
公开(公告)日：2013-02-19
申请号：US13067281
申请日：2011-05-20
申请人： Hideo Tanabe , Masaru Takabatake , Toshiki Kaneko , Atsushi Hasegawa , Hiroko Sehata
发明人： Hideo Tanabe , Masaru Takabatake , Toshiki Kaneko , Atsushi Hasegawa , Hiroko Sehata
IPC分类号： H01L21/00
CPC分类号： G02F1/133345 , G02F1/133305 , G02F1/133504 , G02F1/133555 , G02F1/134363 , G02F1/136213 , G02F1/136227 , G02F1/1368 , G02F2001/13685 , H01L27/124 , H01L27/1248 , H01L29/78675
摘要： The present invention provides a liquid crystal display device having a large holding capacitance in the inside of a pixel. A liquid crystal display device includes a first substrate, a second substrate arranged to face the first substrate in an opposed manner, and liquid crystal sandwiched between the first substrate and the second substrate. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode thereof connected to the video signal line and a second electrode thereof connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film formed above the first silicon nitride film, a capacitance electrode formed above the organic insulation film, and a second silicon nitride film formed above the capacitance electrode and below the pixel electrode. The second silicon nitride film is a film which is formed at a temperature lower than a forming temperature of the first silicon nitride film. The first silicon nitride film and the second silicon nitride film form a contact hole therein by etching both of the first silicon nitride film and the second silicon nitride film collectively by dry etching. The second electrode and the pixel electrode are connected to each other via the contact hole. A potential different from a potential applied to the pixel electrode is applied to the capacitance electrode, and a holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
摘要翻译：本发明提供一种在像素内部具有大的保持电容的液晶显示装置。液晶显示装置包括第一基板，以相对的方式与第一基板相对地布置的第二基板和夹在第一基板和第二基板之间的液晶。第一基板包括视频信号线，像素电极，具有连接到视频信号线的第一电极的薄膜晶体管和连接到像素电极的第二电极，形成在第二电极上方的第一氮化硅膜，形成在第一氮化硅膜上方的有机绝缘膜，形成在有机绝缘膜上方的电容电极和形成在电容电极上方和像素电极下方的第二氮化硅膜。第二氮化硅膜是在低于第一氮化硅膜的形成温度的温度下形成的膜。第一氮化硅膜和第二氮化硅膜通过干法蚀刻同时蚀刻第一氮化硅膜和第二氮化硅膜两者而形成接触孔。第二电极和像素电极经由接触孔相互连接。将施加到像素电极的电位不同的电位施加到电容电极，并且由像素电极，第二氮化硅膜和电容电极形成保持电容。

58. 发明授权

US08363047B2 Active matrix display device 有权
标题翻译：主动矩阵显示装置
公开(公告)号：US08363047B2
公开(公告)日：2013-01-29
申请号：US13437237
申请日：2012-04-02
申请人： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masashiro Maki , Kazutaka Goto
发明人： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masashiro Maki , Kazutaka Goto
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
摘要： A display device includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.
摘要翻译：显示装置包括以稳定的方式操作并且可以扩大设计自由度的动态无比移位寄存器。在具有在衬底表面上由p-Si制成的半导体层的薄膜晶体管的动态无量纲移位寄存器中，通过电容元件将成为浮置状态的节点连接到固定电位。

59. 发明申请

US20120299028A1 MANUFACTURING METHOD FOR LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置的制造方法
公开(公告)号：US20120299028A1
公开(公告)日：2012-11-29
申请号：US13568672
申请日：2012-08-07
申请人： Hideo TANABE , Masaru Takabatake , Toshiki Kaneko , Atsushi Hasegawa , Hiroko Sehata
发明人： Hideo TANABE , Masaru Takabatake , Toshiki Kaneko , Atsushi Hasegawa , Hiroko Sehata
IPC分类号： H01L33/62
CPC分类号： G02F1/133345 , G02F1/133305 , G02F1/133504 , G02F1/133555 , G02F1/134363 , G02F1/136213 , G02F1/136227 , G02F1/1368 , G02F2001/13685 , H01L27/124 , H01L27/1248 , H01L29/78675
摘要： A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
摘要翻译：具有大像素保持电容的LCD装置包括相对的第一和第二基板以及它们之间的液晶。第一基板包括视频信号线，像素电极，具有连接到视频信号线的第一电极的薄膜晶体管和连接到像素电极的第二电极，形成在第二电极上方的第一氮化硅膜，有机物第一氮化硅膜上方的绝缘膜，有机绝缘膜上方的电容电极，以及电容电极上方和像素电极下方的第二氮化硅膜。在第一和第二氮化硅膜中蚀刻的接触孔将第二电极和像素电极彼此连接。保持电容由像素电极，第二氮化硅膜和电容电极形成。

60. 发明授权

US08265471B2 Lens barrel and imaging device 有权
标题翻译：镜筒和成像装置
公开(公告)号：US08265471B2
公开(公告)日：2012-09-11
申请号：US12835748
申请日：2010-07-14
申请人： Atsushi Hasegawa , Tetsuya Uno
发明人： Atsushi Hasegawa , Tetsuya Uno
IPC分类号： G03B17/00
CPC分类号： G03B17/00 , G02B7/102 , Y10T403/33
摘要： The lens barrel includes a first supporting frame, an optical element, a second supporting frame, and a guide shaft. The first supporting frame has a first base portion and a first seat portion that projects in a first direction from the first base portion. The second supporting frame supports the optical element and has a first bearing portion. The guide shaft is coupled to the first seat portion and inserted into the first bearing portion. The first seat portion is disposed within the circumference of the guide shaft when viewed in the first direction.
摘要翻译：镜筒包括第一支撑框架，光学元件，第二支撑框架和导向轴。第一支撑框架具有从第一基部向第一方向突出的第一基部和第一座部。第二支撑框架支撑光学元件并具有第一轴承部分。引导轴联接到第一座椅部分并插入第一轴承部分。当从第一方向观察时，第一座部分布置在引导轴的圆周内。

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