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51. 发明申请

US20120153503A1 CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 有权
公开(公告)号：US20120153503A1
公开(公告)日：2012-06-21
申请号：US13407933
申请日：2012-02-29
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/522
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

52. 发明申请

US20110101538A1 CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 失效
标题翻译：创造不同深度的VIAS和TRENCHES
公开(公告)号：US20110101538A1
公开(公告)日：2011-05-05
申请号：US12610624
申请日：2009-11-02
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。还提供了由此制成的半导体结构。

53. 发明申请

US20110084403A1 PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT 有权
标题翻译：使用自对准的衬垫进行粘合增强的PAD结合
公开(公告)号：US20110084403A1
公开(公告)日：2011-04-14
申请号：US12575980
申请日：2009-10-08
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.
摘要翻译：将两个基材放在一起并放置在电镀浴中。在一个实施例中，将导电材料电镀在存在于第一金属焊盘和第二金属焊盘之间的界面处的微观空腔中，以形成粘附到第一金属焊盘的表面的至少一个界面电镀金属衬垫部分，第二个金属垫。在另一个实施例中，至少一个金属焊盘相对于电介质表面在被聚集之前是凹进的。将两个基板放置在电镀槽中，并且将导电材料镀在第一金属焊盘和第二金属焊盘之间的空腔中，以形成附着在第一金属焊盘的表面上的连续的电镀金属衬垫层，第二个金属垫。

54. 发明申请

US20090278258A1 INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME 有权
标题翻译：带有MUSHROOM型氧化物覆盖层的互连结构及其制造方法
公开(公告)号：US20090278258A1
公开(公告)日：2009-11-12
申请号：US12115944
申请日：2008-05-06
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.
摘要翻译：提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征。本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在第一电介质盖58。

55. 发明授权

US08907458B2 Creation of vias and trenches with different depths 有权
公开(公告)号：US08907458B2
公开(公告)日：2014-12-09
申请号：US13407933
申请日：2012-02-29
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/311
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

56. 发明授权

US08637400B2 Interconnect structures and methods for back end of the line integration 失效
标题翻译：用于线路集成后端的互连结构和方法
公开(公告)号：US08637400B2
公开(公告)日：2014-01-28
申请号：US13164940
申请日：2011-06-21
申请人： David V. Horak , Charles W. Koburger , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Charles W. Koburger , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/31 , H01L23/52
CPC分类号： G06F17/5077 , H01L21/76834 , H01L21/76885
摘要： A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.
摘要翻译：形成半导体结构的方法包括形成牺牲导电材料层。该方法还包括在牺牲导电材料层中形成沟槽。该方法还包括在沟槽中形成导电特征。该方法还包括去除对导电特征有选择性的牺牲导电材料层。该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层中。

57. 发明授权

US08558284B2 Integrated circuit line with electromigration barriers 失效
标题翻译：集成电路线与电迁移障碍
公开(公告)号：US08558284B2
公开(公告)日：2013-10-15
申请号：US13424651
申请日：2012-03-20
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L27/10
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

58. 发明授权

US08492265B2 Pad bonding employing a self-aligned plated liner for adhesion enhancement 有权
标题翻译：使用自对准电镀衬垫的衬垫粘合剂用于粘附增强
公开(公告)号：US08492265B2
公开(公告)日：2013-07-23
申请号：US13431254
申请日：2012-03-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.
摘要翻译：将两个基材放在一起并放置在电镀浴中。在一个实施例中，将导电材料电镀在存在于第一金属焊盘和第二金属焊盘之间的界面处的微观空腔中，以形成粘附到第一金属焊盘表面的至少一个界面电镀金属衬垫部分，第二个金属垫。在另一个实施例中，至少一个金属焊盘相对于电介质表面在被聚集之前是凹进的。将两个基板放置在电镀槽中，并且将导电材料镀在第一金属焊盘和第二金属焊盘之间的空腔中，以形成附着在第一金属焊盘的表面上的连续的电镀金属衬垫层，第二个金属垫。

59. 发明授权

US08354751B2 Interconnect structure for electromigration enhancement 有权
标题翻译：用于电迁移增强的互连结构
公开(公告)号：US08354751B2
公开(公告)日：2013-01-15
申请号：US12139704
申请日：2008-06-16
申请人： David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.
摘要翻译：提供具有增强的电迁移阻力的互连结构，其中通路孔的下部包括多层衬垫。多层衬垫包括从电介质材料的图案化表面向外扩散阻挡层，多材料层和含金属硬掩模。多材料层包括由下面的电介质覆盖层的残留物构成的第一材料层和由下面的金属覆盖层的残留物构成的第二材料层。本发明还提供一种制造这种互连结构的方法，其包括在介电材料内形成的通路孔的下部内的多层衬垫。

60. 发明申请

US20120104619A1 SUBLITHOGRAPHIC PATTERNING EMPLOYING IMAGE TRANSFER OF A CONTROLLABLY DAMAGED DIELECTRIC SIDEWALL 失效
标题翻译：利用控制型电介质边界进行图像传输的分层图案
公开(公告)号：US20120104619A1
公开(公告)日：2012-05-03
申请号：US12913116
申请日：2010-10-27
申请人： Shom Ponoth , David V. Horak , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/02126 , H01L21/3105 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.
摘要翻译：第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和随后在互连级介电材料层中形成线沟槽。

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