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51. 发明专利

JP2007005764A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007005764A
公开(公告)日：2007-01-11
申请号：JP2006086553
申请日：2006-03-27
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , KACHI TORU , UESUGI TSUTOMU , UEDA HIROYUKI , SOEJIMA SHIGEMASA
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/207 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/2003 , H01L29/66462 , H01L29/7787 , H01L29/7788 , H01L29/7828 , H01L29/7832
摘要： PROBLEM TO BE SOLVED: To suppress the diffusion of a p-type impurity (typically magnesium) contained in a semiconductor region of a III-V compound semiconductor into another adjacent semiconductor region. SOLUTION: A semiconductor device 10 comprises a first semiconductor region 28 of gallium nitride (GaN) doped with magnesium which is a p-type impurity, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression film 32 which is interposed between the first semiconductor region 28 and the second semiconductor region 34 and made of silicon oxide (SiO 2 ). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制III-V族化合物半导体的半导体区域中包含的p型杂质（通常为镁）扩散到另一相邻的半导体区域。解决方案：半导体器件10包括掺杂有作为p型杂质的镁的氮化镓（GaN）的第一半导体区域28，氮化镓的第二半导体区域34和杂质扩散抑制膜32 插入在第一半导体区域28和第二半导体区域34之间并由氧化硅（SiO 2 ）制成。版权所有（C）2007，JPO＆INPIT

52. 发明专利

JP2007115861A Hetero junction transistor 审中-公开
标题翻译：异位晶体管
公开(公告)号：JP2007115861A
公开(公告)日：2007-05-10
申请号：JP2005305167
申请日：2005-10-20
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , KACHI TORU , UESUGI TSUTOMU , UEDA HIROYUKI , SOEJIMA SHIGEMASA , KANECHIKA MASAKAZU , KIGAMI MASAHITO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To reduce variation in threshold voltages of the gate of a hetero junction transistor.
SOLUTION: A hetero junction transistor 10 has such structure as an embedded semiconductor region 24, an upper surface embedded insulating film 34, a first semiconductor region 42, a second semiconductor region 44, and a gate electrode 48, are sequentially formed. The embedded semiconductor region 24 is n-type gallium nitride (GaN) electrically insulated from a surrounding semiconductor region. The first semiconductor region 42 is formed from gallium nitride (GaN). The second semiconductor region 44 is formed from gallium nitride-aluminum (Al
0.3 Ga
0.7 N), with its band gap being wider than that of the first semiconductor region 42. A control electrode 26 is electrically connected to the embedded semiconductor region 24.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：减少异质结晶体管的栅极的阈值电压的变化。解决方案：异质结晶体管10具有如下嵌入式半导体区域24，上表面嵌入绝缘膜34，第一半导体区域42，第二半导体区域44和栅极电极48的结构。嵌入式半导体区域24是与周围半导体区域电绝缘的n型氮化镓（GaN）。第一半导体区域42由氮化镓（GaN）形成。第二半导体区域44由氮化镓铝（Al 0.3 S> 0.7 N）形成，其带隙比第一半导体区域42宽。控制电极26电连接到嵌入式半导体区域24.版权所有（C）2007，JPO＆INPIT

53. 发明专利

JP2006140368A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006140368A
公开(公告)日：2006-06-01
申请号：JP2004330123
申请日：2004-11-15
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , UEDA HIROYUKI , SOEJIMA SHIGEMASA , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/80 , H01L21/338 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/812 , H01L29/861
CPC分类号： H01L29/7788 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0843 , H01L29/0847 , H01L29/0891 , H01L29/2003 , H01L29/41 , H01L29/778 , H01L29/7802 , H01L29/8122
摘要： PROBLEM TO BE SOLVED: To suppress the reduction of a withstand voltage or the generation of a leakage current in a semiconductor device with a semiconductor layer in which there is a crystal defect.
SOLUTION: The semiconductor device has a drain electrode 22 connected to one polarity of a power supply and a semiconductor substrate 32. A current control layer 42 covering the surface of the semiconductor substrate 32 while leaving an uncovered region 55 and the semiconductor layers (a drift layer 56, a channel layer 54 and a source layer 52) covering the surface of the current control layer 42. The semiconductor device further has a source electrode 62 formed on the surface of the source layer 52 and connected to the other polarity of the power supply.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制具有晶体缺陷的半导体层的半导体器件中的耐压降低或漏电流的产生。解决方案：半导体器件具有连接到电源和半导体衬底32的一个极性的漏电极22.覆盖半导体衬底32的表面同时留下未覆盖区域55的电流控制层42和半导体层（漂移层56，沟道层54和源极层52）覆盖电流控制层42的表面。半导体器件还具有形成在源极层52的表面上并连接到另一极性的源电极62 的电源。版权所有（C）2006，JPO＆NCIPI

54. 发明专利

JP2006032749A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006032749A
公开(公告)日：2006-02-02
申请号：JP2004210989
申请日：2004-07-20
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , KACHI TORU , NAKANO YOSHITAKA , UESUGI TSUTOMU , UEDA HIROYUKI , SOEJIMA SHIGEMASA
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L29/20 , H01L29/778
CPC分类号： H01L29/778 , H01L21/28 , H01L29/2003 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： PROBLEM TO BE SOLVED: To realize stable normally-off performance in a semiconductor device which has a hetero structure and is constituted of a group III-V compound semiconductor. SOLUTION: In semiconductor device, a p-GaN layer 32, an SI-GaN layer 62 and an AlGaN layer 34 are laminated. The device has a gate electrode 44 which is subjected to Schottky connection in the front side of the AlGaN layer 34. The band gap of the AlGaN layer 34 is larger than that of the p-GaN layer 32 and the SI-GaN layer 62, and the impurity concentration of the SI-GaN layer 62 is ≤1×10 17 cm -3 . COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在具有异质结构并由III-V族化合物半导体构成的半导体器件中实现稳定的常态性能。解决方案：在半导体器件中，层叠p-GaN层32，SI-GaN层62和AlGaN层34。器件具有在AlGaN层34的前侧经肖特基连接的栅电极44.AlGaN层34的带隙大于p-GaN层32和SI-GaN层62的带隙，并且SI-GaN层62的杂质浓度为≤1×10 17 cm -3 。版权所有（C）2006，JPO＆NCIPI

55. 发明专利

JP2008021756A Group iii nitride semiconductor device 审中-公开
标题翻译： III类氮化物半导体器件
公开(公告)号：JP2008021756A
公开(公告)日：2008-01-31
申请号：JP2006191100
申请日：2006-07-12
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , KACHI TORU , UESUGI TSUTOMU , UEDA HIROYUKI , KIGAMI MASAHITO , SOEJIMA SHIGEMASA , HAYASHI EIKO , KANECHIKA MASAKAZU
IPC分类号： H01L29/12 , H01L21/28 , H01L21/338 , H01L29/417 , H01L29/778 , H01L29/78 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To crystal-grow an n- or i-type group III nitride semiconductor on the surface of a p-type group III nitride semiconductor, and to expose the surface of the p-type group III nitride semiconductor without etching a part of the n- or i-type group III nitride semiconductor.
SOLUTION: An impurity diffusion preventing film 36 is provided on a part of the surface of a first group III nitride semiconductor region 28 containing a p-type impurity. An n-type impurity-containing or i-type second group III nitride semiconductor region 44 is provided on a position where it is opposite to the first group III nitride semiconductor region 28 with the interposition of the preventing film 36. Also, a p-type impurity-containing third group III nitride semiconductor region 30 is provided on a position where it is opposite to the first group III nitride semiconductor region 28 without the interposition of the preventing film 36.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在p型III族氮化物半导体的表面上晶体生长n型或i型III族氮化物半导体，并露出p型III族氮化物半导体的表面而不蚀刻n型或i型III族氮化物半导体的一部分。解决方案：在包含p型杂质的第一III族氮化物半导体区域28的表面的一部分上设置杂质扩散防止膜36。通过插入防止膜36，在与第一III族氮化物半导体区域28相反的位置处设置n型杂质或i型第二III族氮化物半导体区域44。含有杂质的第三III族氮化物半导体区域30设置在与第一III族氮化物半导体区域28相对的位置，而不插入防止膜36.版权所有：（C）2008，JPO＆INPIT

56. 发明专利

JP2007273597A Manufacturing method for group iii nitride-based compound semiconductor element 有权
标题翻译：用于III类氮化物的化合物半导体元件的制造方法
公开(公告)号：JP2007273597A
公开(公告)日：2007-10-18
申请号：JP2006095395
申请日：2006-03-30
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UEDA HIROYUKI , KANECHIKA MASAKAZU , SOEJIMA SHIGEMASA , UESUGI TSUTOMU , ISHIGURO OSAMU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L21/338 , H01L21/205 , H01L21/331 , H01L29/737 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To provide a field-effect transistor manufacturing method that utilizes diffusion of magnesium from a lower layer.
SOLUTION: When epitaxial growth is performed so as to form a GaN layer without introducing an Mg material while covering a part of the surface of a p-type layer 1p with a mask layer 2m; a p-body layer 4p is formed at a part contacting with the p-type layer 1p of the lower layer due to dispersion of Mg from the p-type layer 1p, and a channel forming layer 4i composed of undoped GaN is formed in the upper part of the mask layer 2m. Similarly, a p-AlGaN layer 5p is formed in the upper part of the p-body layer 4p due to dispersion of Mg from the p-body layer 4p, and an undoped AlGaN layer 5i is formed in the upper part of the channel forming layer 4i. A HEMT 100 formed in such a manner as described above has excellent ohmic properties since the surface of the p-AlGaN layer 5p, on which a body electrode Bd is formed, is not subjected to etching processing and is capable of stably maintaining potential of the channel forming layer 4i from the body electrode Bd via the p-AlGaN layer 5p and the p-body layer 4p so as to become an element with stable element characteristics.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供利用来自下层的镁的扩散的场效应晶体管制造方法。解决方案：当进行外延生长以形成GaN层而不引入Mg材料同时用掩模层2m覆盖p型层1p的一部分表面时; 由于由p型层1p分散Mg而在与下层的p型层1p接触的部分形成p体层4p，在p型层1p中形成由未掺杂的GaN构成的沟道形成层4i 掩模层2m的上部。类似地，由于由p体层4p分散Mg而在p体层4p的上部形成p-AlGaN层5p，并且在沟道形成的上部形成未掺杂的AlGaN层5i 层4i。以上述方式形成的HEMT 100由于形成有体电极Bd的p-AlGaN层5p的表面不进行蚀刻处理而能够稳定地保持电位，因此具有优异的欧姆特性沟道形成层4i经由p-AlGaN层5p和p体层4p从体电极Bd成为具有稳定元件特性的元件。版权所有（C）2008，JPO＆INPIT

57. 发明专利

JP2007250955A Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：JP2007250955A
公开(公告)日：2007-09-27
申请号：JP2006074211
申请日：2006-03-17
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , SOEJIMA SHIGEMASA , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/786 , H01L21/336 , H01L21/338 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7788
摘要： PROBLEM TO BE SOLVED: To dissolve the generation insufficiency of a two-dimensional electron gas layer near a source electrode.
SOLUTION: The thickness of a first non p-type layer 104 is non-uniform due to the formation of a projection (center part 103a). That is, since the pn junction interface of a p-type semiconductor crystal layer 103 and the first non p-type layer 104 is raised higher than the other part under a gate electrode G, the thickness of the first non p-type layer 104 is thinner than the other part under the gate electrode G. Also, the end of the thick film of the first non p-type layer 104 is extended so as to burrow right under the peripheral edge of a gate insulation film 106. Then, by the structure, the upper end face α of a depletion layer including a pn junction interface does not reach the interface of the first non p-type layer 104 and a second non p-type layer 105 near respective electrodes S and D for conduction. Also, the upper end face α of the depletion layer enters the inside of the second non p-type layer 105 under the gate electrode G.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了溶解源电极附近的二维电子气层的产生不足。解决方案：由于形成突起（中心部分103a），第一非p型层104的厚度是不均匀的。也就是说，由于p型半导体晶体层103和第一非p型层104的pn结界面比栅电极G下方的其他部分升高，所以第一非p型层104的厚度比栅极电极G下方的其他部分薄。另外，第一非p型层104的厚膜的端部延伸，以便在栅极绝缘膜106的外围边缘下方挖洞。然后，通过结构中，包括pn结界面的耗尽层的上端面α不会到达第一非p型层104和靠近各个电极S和D的导电的第二非p型层105的界面。此外，耗尽层的上端面α进入栅电极G下方的第二非p型层105的内部。版权所有（C）2007，JPO＆INPIT

58. 发明专利

JP2006196552A Junction field effect transistor 审中-公开
标题翻译：连接场效应晶体管
公开(公告)号：JP2006196552A
公开(公告)日：2006-07-27
申请号：JP2005004492
申请日：2005-01-11
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , UEDA HIROYUKI , SOEJIMA SHIGEMASA , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/808 , H01L21/337
摘要： PROBLEM TO BE SOLVED: To provide a junction field effect transistor in which a high gate voltage can be utilized and in which an on-stage resistance is reduced in the junction field effect transistor.
SOLUTION: The junction field effect transistor includes a channel semiconductor region 34 located between a source electrode S and a drain electrode D, and made of an n-GaN in which electron moves; a gate semiconductor region 32 adjoining the channel semiconductor region 34, and made of a p-Al
O.3 Ga
O.7 N having a band gap larger than the band gap of the channel semiconductor region 34; and a gate electrode G which contacts the gate semiconductor region 32 electrically.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种结型场效应晶体管，其中可以利用高栅极电压并且在场效应晶体管中降低阶段电阻。结型场效应晶体管包括：位于源电极S和漏电极D之间的沟道半导体区域34，由电子移动的n-GaN构成; 与沟道半导体区域34邻接并由具有比带隙大的带隙的p-Al 3 S 3 O 3 / N 2 O 7 N N的栅极半导体区域32 的沟道半导体区域34; 以及与栅极半导体区域32电接触的栅极电极G. 版权所有（C）2006，JPO＆NCIPI

59. 发明专利

JP2006114802A Structure with upper layer laminated on group iii-v semiconductor layer and its manufacturing method 有权
标题翻译：上层层叠在III-V族半导体层上的结构及其制造方法
公开(公告)号：JP2006114802A
公开(公告)日：2006-04-27
申请号：JP2004302514
申请日：2004-10-18
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KIGAMI MASAHITO , HAYASHI EIKO , SOEJIMA SHIGEMASA , SUGIMOTO MASAHIRO
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method capable of removing a gallium oxide film formed on the surface as a natural oxide film without damaging the surface of a GaN layer 24 in manufacturing a structure with the upper layer laminated on the surface of the GaN layer 24.
SOLUTION: This method manufactures a structure where an SiO
2 layer 26 made of oxide silicon is laminated on the surface of a GaN layer 24. It comprises a process for exposing the surface of the GaN layer 24 to gas including non-plasma ammonia, and a process for laminating the SiO
2 layer 26 on the surface of the GaN layer 24 exposed to the ammonia gas.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够除去形成在表面上的氧化镓膜作为天然氧化物膜的方法，而不会在制造具有层叠在表面上的上层的结构的GaN层24的表面上 GaN层24.解决方案：该方法制造其中由氧化硅制成的SiO 2 SB 2层26层压在GaN层24的表面上的结构。它包括一种将包括非等离子体氨的气体的GaN层24的表面，以及暴露于氨气的GaN层24的表面上层叠SiO 2 SB 2层26的工序。版权所有（C）2006，JPO＆NCIPI

60. 发明专利

JP2014110305A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2014110305A
公开(公告)日：2014-06-12
申请号：JP2012263471
申请日：2012-11-30
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： TSUJIMURA MASATOSHI , FUJIWARA HIROKAZU , MORINO TOMOO , SOEJIMA SHIGEMASA
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/046 , H01L21/67303 , H01L29/1608
摘要： PROBLEM TO BE SOLVED: To provide an art to inhibit roughening of a wafer surface caused by Si atom desorption from a surface of a silicon carbide wafer in a heat treatment process of a semiconductor device and increase production efficiency of the semiconductor device.SOLUTION: A semiconductor device manufacturing method disclosed in the present embodiment comprises an arrangement process and a heat treatment process. In the arrangement process, a plurality of silicon carbide wafers 10 each including a first surface 16 and a second surface 18 which is a rear face of the first surface in a manner such that the centers of the silicon carbide wafers 10 are coaxially located and the first surface 16 and the second surface 18 of the adjacent silicon carbide wafers are opposite to each other and separated in parallel with each other. In the heat treatment process, the plurality of silicon carbide wafers 10 arranged in the arrangement process are heated in a manner such that a temperature of the first surface 16 of each silicon carbide wafer becomes higher than that of the second surface 18 and a temperature of the second surface 18 of one silicon carbide wafer 10 between the adjacent silicon carbide wafers 10 becomes higher than that of the first surface 16 of the other silicon carbide wafer which is opposite to the second surface 18.
摘要翻译：要解决的问题：提供一种在半导体器件的热处理工艺中抑制由硅化物晶片的表面Si原子解吸引起的晶片表面粗糙化的技术，并提高半导体器件的生产效率。解决方案：A 本实施例中公开的半导体器件制造方法包括布置处理和热处理工艺。在排列过程中，多个碳化硅晶片10各自包括第一表面16和第二表面18，第二表面18是第一表面的后表面，其方式使得碳化硅晶片10的中心位于同轴位置，并且相邻的碳化硅晶片的第一表面16和第二表面18彼此相对并且彼此平行地分离。在热处理工序中，以配置方式配置的多个碳化硅晶片10的加热方式使得每个碳化硅晶片的第一表面16的温度变得高于第二表面18的温度，在相邻碳化硅晶片10之间的一个碳化硅晶片10的第二表面18变得高于与第二表面18相对的另一个碳化硅晶片的第一表面16的第二表面18。

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