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51. 发明授权

US07504297B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07504297B2
公开(公告)日：2009-03-17
申请号：US11723344
申请日：2007-03-19
申请人： Kozo Watanabe , Shoji Yoshida , Masashi Sahara , Shinichi Tanabe , Takashi Hashimoto
发明人： Kozo Watanabe , Shoji Yoshida , Masashi Sahara , Shinichi Tanabe , Takashi Hashimoto
IPC分类号： H01L21/8234
CPC分类号： H01L29/872 , H01L27/0629 , H01L28/20 , H01L29/7833
摘要： A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSi2 layer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.
摘要翻译：提供了一种技术，其中可以在同一芯片中形成高性能肖特基势垒二极管和其他半导体元件，以控制步骤数量的增加。在氧化硅膜沉积在其上形成n沟道型MISFET的衬底上并且选择性地去除栅电极和n +型半导体区上的氧化硅膜之后，在衬底上沉积Co膜，并且CoSi 2层是通过对基板进行热处理而形成在n +型半导体区域和栅电极之上。在氮化硅膜沉积在衬底上之后，通过去除肖特基势垒二极管的阳极形成部分处的氮化硅膜和氧化硅膜来形成到达衬底的孔径，在衬底上沉积Ti膜在孔的内侧，通过对基板进行热处理，在孔的底部形成成为肖特基势垒二极管的阳极的TiSi 2层。

52. 发明授权

US07397104B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07397104B2
公开(公告)日：2008-07-08
申请号：US10778081
申请日：2004-02-17
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L21/00
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
摘要翻译：提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半。

53. 发明授权

US07348245B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07348245B2
公开(公告)日：2008-03-25
申请号：US11443257
申请日：2006-05-31
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L21/8234
CPC分类号： H01L27/11568 , G11C11/005 , G11C16/0466 , H01L27/105 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.
摘要翻译：一种半导体器件的制造方法，用于形成包括用于存储器的第一场效应晶体管的可重写非易失性存储单元，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，包括在半导体衬底上形成栅极绝缘膜栅极绝缘膜上的栅电极和与第一至第三场效应晶体管中的每一个相关联的栅电极的侧壁上的侧壁隔离物。至少第一场效应晶体管的侧壁间隔物具有与至少第二场效应晶体管不同的宽度，第三场效应晶体管的栅电极具有与至少第一场效应晶体管不同的长度，存储器和第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的厚度。

54. 发明申请

US20060281007A1 Lithium ion secondary battery and method for manufacturing same 失效
标题翻译：锂离子二次电池及其制造方法
公开(公告)号：US20060281007A1
公开(公告)日：2006-12-14
申请号：US10569368
申请日：2005-05-12
申请人： Shuji Tsutsumi , Kozo Watanabe , Mitsuhiro Takeno , Mikinari Shimada
发明人： Shuji Tsutsumi , Kozo Watanabe , Mitsuhiro Takeno , Mikinari Shimada
IPC分类号： H01M2/18 , H01M4/58 , H01M4/48 , H01M10/04
CPC分类号： H01M10/0525 , H01M2/18 , H01M4/13 , H01M4/131 , H01M4/133 , H01M4/62 , H01M10/0587 , H01M10/4235 , H01M2004/025 , Y10T29/49108 , Y10T29/49115
摘要： A lithium ion secondary battery with improved safety against both internal short-circuiting and overcharge is provided. This lithium ion secondary battery includes a positive electrode comprising a composite lithium oxide, a negative electrode, and a non-aqueous electrolyte. At least one of the positive electrode and the negative electrode has a porous film, comprising an inorganic oxide filler and a binder, on the surface facing the other electrode, and the electrode surface having the porous film partially has a protruded part. This protruded part may be a protruded part formed on the porous film itself or a protruded part formed on an electrode mixture layer. Further, a separator can also be incorporated therein. Instead of the above-mentioned porous film, the separator can be provided with a porous film.
摘要翻译：提供一种具有改善内部短路和过充电的安全性的锂离子二次电池。该锂离子二次电池包括含有复合氧化锂，负极和非水电解质的正极。正电极和负电极中的至少一个在面向另一个电极的表面上具有包含无机氧化物填充剂和粘合剂的多孔膜，并且具有多孔膜的电极表面部分地具有突出部分。该突出部分可以是形成在多孔膜本身上的突出部分或形成在电极混合物层上的突出部分。此外，还可以并入隔板。代替上述多孔膜，隔板可以设置有多孔膜。

55. 发明申请

US20060214256A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214256A1
公开(公告)日：2006-09-28
申请号：US11443252
申请日：2006-05-31
申请人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
发明人： Masaaki Shinohara , Kozo Watanabe , Fukuo Owada , Takashi Aoyama
IPC分类号： H01L29/00
CPC分类号： H01L27/11568 , H01L27/115
摘要： A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor. The sidewall spacers of the first field effect transistor include a first silicon oxide film, a first silicon nitride film over the first silicon oxide film and a second silicon oxide film over the first silicon nitride film.
摘要翻译：一种半导体器件，具有可重写非易失性存储单元，其包括用于存储的第一场效应晶体管，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，所述晶体管包括形成在半导体衬底上的栅极绝缘膜，在栅极绝缘膜上方的栅电极和相应栅电极的侧壁上的侧壁间隔物。第一场效应晶体管的侧壁间隔物与至少第二场效应晶体管的侧壁间隔物不同。此外，第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的栅极绝缘膜，第三场效应晶体管的栅电极的长度与第一场效应晶体管或第二场效应晶体管的长度不同效应晶体管。第一场效应晶体管的侧壁间隔物包括第一氧化硅膜，第一氧化硅膜上的第一氮化硅膜和位于第一氮化硅膜上的第二氧化硅膜。

56. 发明申请

US20060133146A1 Semiconductor device and a method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060133146A1
公开(公告)日：2006-06-22
申请号：US11297392
申请日：2005-12-09
申请人： Keiichi Maekawa , Shinichi Minami , Kozo Watanabe , Shiro Kamohara , Shoji Yoshida
发明人： Keiichi Maekawa , Shinichi Minami , Kozo Watanabe , Shiro Kamohara , Shoji Yoshida
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/3418 , G11C16/3427 , H01L29/66833 , H01L29/792
摘要： A semiconductor device having a well region of a first conduction type formed in a main surface of a semiconductor substrate, and a nonvolatile memory element formed at the well region is provided. The nonvolatile memory element comprises a gate electrode formed over the well region through an insulating film for charge storage, and a source region and drain region of a second conduction type which are separated from each other and are disposed in the well region. The well region includes a third semiconductor region, a second semiconductor region which is arranged at a position deeper than the third semiconductor region, and a first semiconductor region that is arranged at a position deeper than the second semiconductor region. The first and third semiconductor regions, respectively, have an impurity concentration higher than the second semiconductor region.
摘要翻译：提供一种形成在半导体衬底的主表面中的具有第一导电类型的阱区域的半导体器件和形成在阱区域的非易失性存储元件。非易失性存储元件包括通过用于电荷存储的绝缘膜在阱区上形成的栅电极，以及彼此分离并设置在阱区中的第二导电类型的源极区和漏极区。阱区域包括第三半导体区域，布置在比第三半导体区域更深的位置处的第二半导体区域以及布置在比第二半导体区域更深的位置的第一半导体区域。第一和第三半导体区域分别具有高于第二半导体区域的杂质浓度。

57. 发明申请

US20060115730A1 Non-aqueous electrolyte secondary battery 有权
标题翻译：非水电解质二次电池
公开(公告)号：US20060115730A1
公开(公告)日：2006-06-01
申请号：US11262927
申请日：2005-11-01
申请人： Akihiro Taniguchi , Kohei Suzuki , Shuji Tsutsumi , Mitsuhiro Takeno , Kozo Watanabe , Takashi Takeuchi , Takaya Saito
发明人： Akihiro Taniguchi , Kohei Suzuki , Shuji Tsutsumi , Mitsuhiro Takeno , Kozo Watanabe , Takashi Takeuchi , Takaya Saito
IPC分类号： H01M4/62 , H01M4/52
CPC分类号： H01M4/525 , H01M4/131 , H01M4/505 , H01M4/621
摘要： Disclosed is a non-aqueous electrolyte secondary battery having an electrode group in which a positive electrode and a negative electrode are spirally wound with a separator interposed therebetween. The positive electrode contains a positive electrode active material and a binder. The positive electrode active material contains a mixture of two different particulate substances having different average particle sizes. The two different particulate substances are lithium composite metal oxides containing nickel as an essential element. The binder includes fluorocarbon resin and rubber particles. The fluorocarbon resin contains at least a vinylidene fluoride unit. The amount of the rubber particles per 100 parts by weight of the fluorocarbon resin is 1 to 25 parts by weight.
摘要翻译：公开了一种具有电极组的非水电解质二次电池，其中正电极和负电极螺旋地缠绕有隔膜。正极含有正极活性物质和粘合剂。正极活性物质含有具有不同平均粒径的两种不同颗粒物质的混合物。两种不同的颗粒物质是含有镍作为必需元素的锂复合金属氧化物。粘合剂包括氟碳树脂和橡胶颗粒。氟碳树脂含有至少一个偏二氟乙烯单元。每100重量份氟碳树脂中的橡胶颗粒的量为1至25重量份。

58. 发明申请

US20050271375A1 Imaging apparatus 审中-公开
标题翻译：成像设备
公开(公告)号：US20050271375A1
公开(公告)日：2005-12-08
申请号：US11131328
申请日：2005-05-18
申请人： Tsuyoshi Watanabe , Kozo Watanabe , Jo Kinoshita
发明人： Tsuyoshi Watanabe , Kozo Watanabe , Jo Kinoshita
IPC分类号： G02B7/02 , G02B7/04 , G02B13/00 , G03B3/00 , H04N5/225 , H04N5/232
CPC分类号： H04N5/23212 , G02B7/022 , G02B7/04 , G02B13/001 , G03B3/00 , H04N5/2254
摘要： An imaging apparatus, comprising a holder having a solid-state image sensor, a lens barrel rotatably engaged with the holder and having an optical device for focusing an image on the solid-state image sensor's acceptance surface, and a focus-adjusting device provided between the lens barrel and the holder, the focus-adjusting device including a cam mechanism capable of changing a distance between the optical device and the solid-state image sensor in response to relative rotation between the holder and the lens barrel, the cam mechanism including plural pairs of controlling parts having a plurality of bearing surfaces disposed on one of the lens barrel and the holder to space out peripherally and projecting in an optical direction of the optical device, and a plurality of receiving surfaces disposed peripherally on the other of the lens barrel and the holder to be positioned at equal intervals, projecting in the optical direction of the optical device and contactable with each of the bearing surfaces.
摘要翻译：一种成像装置，包括具有固态图像传感器的保持器，与保持器可旋转地接合的镜筒，并具有用于将图像聚焦在固态图像传感器的接受表面上的光学装置，以及聚焦调节装置，所述镜筒和所述保持器，所述调焦装置包括能够响应于所述保持器和所述镜筒之间的相对旋转而改变所述光学装置与所述固态图像传感器之间的距离的凸轮机构，所述凸轮机构包括多个成对的控制部件具有设置在透镜镜筒和保持器中的一个上的多个支承表面，用于沿光学装置的光学方向在外围空间和突出;以及多个接收表面，其设置在透镜镜筒的另一个周边并且保持器以相等的间隔定位，在光学装置的光学方向上突出并且可与b中的每一个接触耳朵表面。

59. 发明授权

US06858515B2 Process for producing semiconductor device and semiconductor device produced thereby 失效
标题翻译：由此生产半导体器件和半导体器件的方法
公开(公告)号：US06858515B2
公开(公告)日：2005-02-22
申请号：US10638485
申请日：2003-08-12
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

60. 发明申请

US20050017274A1 Semiconductor integrated circuitry and method for manufacturing the circuitry 有权
标题翻译：半导体集成电路和制造电路的方法
公开(公告)号：US20050017274A1
公开(公告)日：2005-01-27
申请号：US10920389
申请日：2004-08-18
申请人： Kozo Watanabe , Atsushi Ogishima , Masahiro Moniwa , Syunichi Hashimoto , Masayuki Kojima , Kiyonori Ohyu , Kenichi Kuroda , Nozomu Matsuda
发明人： Kozo Watanabe , Atsushi Ogishima , Masahiro Moniwa , Syunichi Hashimoto , Masayuki Kojima , Kiyonori Ohyu , Kenichi Kuroda , Nozomu Matsuda
IPC分类号： H01L21/8242 , H01L27/105 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10852 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10894 , Y10S257/90
摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.
摘要翻译：用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

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