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51. 发明申请

US20060221663A1 Electronic device with a memory cell 有权
标题翻译：具有存储单元的电子设备
公开(公告)号：US20060221663A1
公开(公告)日：2006-10-05
申请号：US11099384
申请日：2005-04-05
申请人： Thomas Roehr
发明人： Thomas Roehr
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0011 , G11C13/003 , G11C2213/75 , G11C2213/76 , G11C2213/79
摘要： The present invention relates to an electronic device comprising a memory cell with a resistive storage element having a first terminal and a second terminal. The resistive storage element can be switched between a first storage state with a first conductivity and a second storage state with a second conductivity. An access switch is coupled to the first terminal of the resistive storage element and to a node for connecting the first terminal of the resistive storage element to the node in an access state of the memory cell and for insulating the first terminal of the resistive storage element from the node in an idle state of the memory cell. A protecting switch is connected to the resistive storage element. The protecting switch, in the idle state of the memory cell, reduces the voltage across the resistive storage element produced by electromagnetic interference and, in the access state of the memory cell, enables the reading and the writing of the storage states of the resistive storage element. The electronic device may further comprise a control circuit operatively coupled to the access switch and to the protective switch which is configured to control the function of the access switch and the protecting switch in the access state and in the idle state of the memory cell.
摘要翻译：本发明涉及一种电子设备，包括具有电阻存储元件的存储单元，该电阻存储元件具有第一端子和第二端子。电阻存储元件可以在具有第一导电性的第一存储状态和具有第二导电性的第二存储状态之间切换。接入开关耦合到电阻存储元件的第一端子和耦合到存储单元的访问状态的用于将电阻存储元件的第一端子连接到节点并将电阻存储元件的第一端子绝缘的节点从存储器单元的空闲状态的节点。保护开关连接到电阻存储元件。在存储器单元的空闲状态下的保护开关降低由电磁干扰产生的电阻存储元件两端的电压，并且在存储单元的访问状态下，能够读取和写入电阻存储器的存储状态元件。电子设备还可以包括可操作地耦合到接入交换机和保护交换机的控制电路，保护交换机被配置为控制接入交换机和保护交换机处于存取单元的接入状态和空闲状态的功能。

52. 发明申请

US20060181916A1 Non-volatile memory cell for storage of a data item in an integrated circuit 有权
公开(公告)号：US20060181916A1
公开(公告)日：2006-08-17
申请号：US11332768
申请日：2006-01-13
申请人： Thomas Roehr
发明人： Thomas Roehr
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009 , G11C17/16 , G11C17/18
摘要： The present invention relates to a non-volatile memory cell for storage of a data item in an integrated circuit, comprising a resistive memory element which may have different conductance states depending on the stored data item, a memory unit for passing the stored data item to an integrated circuit, a read unit which can be activated in order to pass a data item on for storage in the memory unit as a function of the conductance state of the memory element, a control unit in order to activate the read unit so that the data item to be passed on is stored in the memory unit, and in order to deactivate the read unit after storage of the data item in the memory unit, such that the memory element is isolated from the memory unit.

53. 发明申请

US20060062043A1 CBRAM memory cell arrangement and method for programming CBRAM memory cells 有权
标题翻译： CBRAM存储单元布置方法和CBRAM存储单元编程方法
公开(公告)号：US20060062043A1
公开(公告)日：2006-03-23
申请号：US11209424
申请日：2005-08-23
申请人： Thomas Roehr , Ralf Symanczyk , Michael Kund
发明人： Thomas Roehr , Ralf Symanczyk , Michael Kund
IPC分类号： G11C11/24
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/0078
摘要： A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to comprise a charge storage device and a switchable charging apparatus. The inventive method for programming memory cells of the CBRAM type is carried out in such a manner that, a given quantity of an electrical charge is stored in a charge storage device, and the stored quantity of electrical charge is transferred to the memory cell to be programmed.
摘要翻译：存储单元布置具有多个CBRAM类型的存储单元和编程设备，存储器单元沿着位线布置，并且每个位线具有编程设备。本发明提供了编程装置，其包括电荷存储装置和可切换充电装置。用于编写CBRAM类型的存储单元的本发明方法是以一定量的方式进行的，即将一定数量的电荷存储在电荷存储装置中，并将存储的电荷量传送到存储单元程序。

54. 发明申请

US20050276140A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050276140A1
公开(公告)日：2005-12-15
申请号：US10931978
申请日：2004-09-02
申请人： Ryu Ogiwara , Daisaburo Takashima , Thomas Roehr
发明人： Ryu Ogiwara , Daisaburo Takashima , Thomas Roehr
IPC分类号： G11C11/22 , G03B42/02 , G03C5/16 , G11C7/04 , G11C7/14
CPC分类号： G11C7/14 , G03B42/02 , G11C7/04 , G11C11/22
摘要： A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.
摘要翻译：虚拟电容器驱动电位VDC被提供给虚拟电容器的一个电极，并且在其另一个电极中产生用于确定存储器单元的数据值的参考电位。用于产生电位VDC的潜在发电机电路由输出具有温度依赖性的电位VBGRTEMP的BGR电路和串联连接在BGR电路的输出端子与接地点之间的电阻器R 3和R 4构成。从电阻器R 3和R 4的连接点输出电位VDC。电阻VDC的温度依赖性根据电阻器R 1 - 1，R 1 - 2和R 2的电阻比进行调整，并且绝对值根据电阻器R 3和R 4的电阻比进行调整。

55. 发明授权

US06903959B2 Sensing of memory integrated circuits 失效
标题翻译：感应存储器集成电路
公开(公告)号：US06903959B2
公开(公告)日：2005-06-07
申请号：US10065168
申请日：2002-09-24
申请人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
发明人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
IPC分类号： G11C7/06 , G11C7/14 , G11C11/22
CPC分类号： G11C7/14 , G11C7/062 , G11C11/22
摘要： A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
摘要翻译：公开了一种在读取期间具有改进的感测的存储器IC。 IC包括使用第一和第二参考电压进行感测以补偿存在于位线真数和位线补码之间的单元之间的不对称性。第一个参考电压用于在位线真时感测单元，而第二个参考电压用于感测位线补码上的单元。

56. 发明申请

US20050050261A1 High density flash memory with high speed cache data interface 审中-公开
标题翻译：高密度闪存与高速缓存数据接口
公开(公告)号：US20050050261A1
公开(公告)日：2005-03-03
申请号：US10650458
申请日：2003-08-27
申请人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
发明人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
IPC分类号： G06F12/08 , G11C8/12 , G11C16/10 , G06F12/00
CPC分类号： G11C8/12 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/10 , G11C2207/2245
摘要： A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.
摘要翻译：数据存储装置包括控制器，FeRAM存储器单元和具有比FeRAM存储器单元高得多的数据存储容量的闪存单元。最初，当数据存储装置接收到数据时，控制器将其存储在FeRAM存储单元中。这可以非常快速地完成，因为FeRAM器件具有高写入速率。随后，控制器将数据传送到闪存单元。因此，数据存储设备结合了FeRAM器件的高存储容量和闪存器件的高存储容量。

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